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74AHCT574 Datenblatt(PDF) 9 Page - NXP Semiconductors |
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74AHCT574 Datenblatt(HTML) 9 Page - NXP Semiconductors |
9 / 18 page 74AHC_AHCT574_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 24 January 2008 9 of 18 NXP Semiconductors 74AHC574; 74AHCT574 Octal D-type flip-flop; positive edge-trigger; 3-state tsu set-up time Dn to CP; see Figure 8 VCC = 3.0 V to 3.6 V; CL =50pF 3.5 - - 3.5 - 3.5 - ns VCC = 4.5 V to 5.5 V; CL =50pF 3.0 - - 3.0 - 3.0 - ns th hold time Dn to CP; see Figure 8 VCC = 3.0 V to 3.6 V; CL =50pF 1.5 - - 1.5 - 1.5 - ns VCC = 4.5 V to 5.5 V; CL =50pF 1.5 - - 1.5 - 1.5 - ns CPD power dissipation capacitance CL = 50 pF; fi = 1 MHz; VI = GND to VCC [3] -10 - - - - - pF For type 74AHCT574 tpd propagation delay CP to Qn; see Figure 7 [2] VCC = 4.5 V to 5.5 V CL = 15 pF - 4.4 8.6 1.0 10.0 1.0 11.0 ns CL = 50 pF - 6.3 10.6 1.0 12.0 1.0 13.5 ns ten enable time OE to Qn; see Figure 9 VCC = 4.5 V to 5.5 V CL = 15 pF - 4.3 9.0 1.0 10.5 1.0 11.5 ns CL = 50 pF - 6.1 11.0 1.0 12.5 1.0 14.0 ns tdis disable time OE to Qn; see Figure 9 [2] VCC = 4.5 V to 5.5 V CL = 15 pF - 4.3 9.0 1.0 10.5 1.0 11.5 ns CL = 50 pF - 6.2 10.1 1.0 11.5 1.0 13.0 ns fmax maximum frequency CP; see Figure 7 VCC = 4.5 V to 5.5 V CL = 15 pF 130 180 - 110 - 110 - MHz CL = 50 pF 85 115 - 75 - 75 - MHz tW pulse width CP; HIGH or LOW; see Figure 7 VCC = 4.5 V to 5.5 V; CL =50pF 5.0 - - 5.5 - 5.5 - ns tsu set-up time Dn to CP; see Figure 8 VCC = 4.5 V to 5.5 V; CL =50pF 3.0 - - 3.5 - 3.5 - ns Table 7. Dynamic characteristics …continued GND = 0 V. For test circuit see Figure 10. Symbol Parameter Conditions 25 °C −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ[1] Max Min Max Min Max |
Ähnliche Teilenummer - 74AHCT574 |
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Ähnliche Beschreibung - 74AHCT574 |
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