Datenblatt-Suchmaschine für elektronische Bauteile |
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DAC102S085 Datenblatt(PDF) 6 Page - Texas Instruments |
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DAC102S085 Datenblatt(HTML) 6 Page - Texas Instruments |
6 / 28 page DAC102S085 SNAS364E – MAY 2006 – REVISED MARCH 2013 www.ti.com A.C. and Timing Characteristics Values shown in this table are design targets and are subject to change before product release. The following specifications apply for VA = +2.7V to +5.5V, VREFIN = VA, CL = 200 pF to GND, fSCLK = 30 MHz, input code range 12 to 1011. Boldface limits apply for TMIN ≤ TA ≤ TMAX and all other limits are at TA = 25°C, unless otherwise specified. Units Symbol Parameter Conductions Typical(1) Limits(1) (Limits) fSCLK SCLK Frequency 40 30 MHz (max) 100h to 300h code change ts Output Voltage Settling Time(2) 4.5 6 µs (max) RL = 2 kΩ, CL = 200 pF SR Output Slew Rate 1 V/µs Glitch Impulse Code change from 200h to 1FFh 12 nV-sec Digital Feedthrough 0.5 nV-sec Digital Crosstalk 1 nV-sec DAC-to-DAC Crosstalk 3 nV-sec Multiplying Bandwidth VREFIN = 2.5V ± 0.1Vpp 160 kHz VREFIN = 2.5V ± 1.0Vpp Total Harmonic Distortion 70 dB input frequency = 10kHz VA = 3V 6 µsec tWU Wake-Up Time VA = 5V 39 µsec 1/fSCLK SCLK Cycle Time 25 33 ns (min) tCH SCLK High time 7 10 ns (min) tCL SCLK Low Time 7 10 ns (min) SYNC Set-up Time prior to SCLK tSS 4 10 ns (min) Falling Edge Data Set-Up Time prior to SCLK Falling tDS 1.5 3.5 ns (min) Edge Data Hold Time after SCLK Falling tDH 1.5 3.5 ns (min) Edge tCFSR SCLK fall prior to rise of SYNC 0 3 ns (min) tSYNC SYNC High Time 6 10 ns (min) (1) Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are specified to AOQL (Average Outgoing Quality Level). (2) This parameter is specified by design and/or characterization and is not tested in production. 6 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: DAC102S085 |
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