L5973AD

Functional description

Doc ID 9552 Rev 9

9/22

In particular, connecting together two devices, the one with the lower switching frequency

works as Slave and the other one works as Master.

To synchronize the device, the SYNC pin has to pass from a low level to a level higher than

the synchronization threshold with a duty cycle that can vary approximately from 10% to

90%, depending also on the signal frequency and amplitude.

The frequency of the synchronization signal must be at least higher than the internal

switching frequency of the device (500 kHz).

Figure 5.

Oscillator circuit

4.4

Current protection

The L5973AD has two current limit protections, pulse by pulse and frequency fold back.

The schematic of the current limitation circuitry for the pulse by pulse protection is shown in

Figure 6.

The output power PDMOS transistor is split in two parallel PDMOS. The smallest one has a

threshold, the mirror is unbalanced and the PDMOS is switched off until the next falling edge

of the internal clock pulse.

Due to this reduction of the ON time, the output voltage decreases.

Since the minimum switch ON time (necessary to avoid false overcurrent signal) is not

enough to obtain a sufficiently low duty cycle at 500 kHz, the output current, in strong

overcurrent or short circuit conditions, could increase again. For this reason the switching

frequency is also reduced, so keeping the inductor current under its maximum threshold.

The Frequency Shifter (see Figure 5) depends on the feedback voltage. As the feedback

voltage decreases (due to the reduced duty cycle), the switching frequency decreases too.

FREQUENCY

SHIFTER

CLOCK

GENERATOR

RAMP

GENERATOR

SYNCHRONIZATOR

CLOCK

RAMP

Ibias_osc

SYNC

t

D00IN1131