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AD5315ARM Datenblatt(PDF) 1 Page - Analog Devices

Teilenummer AD5315ARM
Bauteilbeschribung  2.5 V to 5.5 V, 500 A, 2-Wire Interface Quad Voltage Output, 8-/10-/12-Bit DACs
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2.5 V to 5.5 V, 500 μA, 2-Wire Interface
Quad Voltage Output, 8-/10-/12-Bit DACs
AD5305/AD5315/AD5325
Rev. G
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringements of patents or other
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
FEATURES
AD5305: 4 buffered 8-bit DACs in 10-lead MSOP
A version: ±1 LSB INL, B version: ±0.625 LSB INL
AD5315: 4 buffered 10-bit DACs in 10-lead MSOP
A version: ±4 LSB INL, B version: ±2.5 LSB INL
AD5325: 4 buffered 12-bit DACs in 10-lead MSOP
A version: ±16 LSB INL, B version: ±10 LSB INL
Low power operation: 500 μA @ 3 V, 600 μA @ 5 V
2-wire (I2C®-compatible) serial interface
2.5 V to 5.5 V power supply
Guaranteed monotonic by design over all codes
Power-down to 80 nA @ 3 V, 200 nA @ 5 V
Three power-down modes
Double-buffered input logic
Output range: 0 V to VREF
Power-on reset to 0 V
Simultaneous update of outputs (LDAC function)
Software clear facility
Data readback facility
On-chip rail-to-rail output buffer amplifiers
Temperature range: −40°C to +105°C
APPLICATIONS
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
Industrial process control
GENERAL DESCRIPTION
The AD5305/AD5315/AD53251 are quad 8-, 10-, and 12-bit
buffered voltage output DACs in a 10-lead MSOP that operate
from a single 2.5 V to 5.5 V supply, consuming 500 μA at 3 V.
Their on-chip output amplifiers allow rail-to-rail output swing
with a slew rate of 0.7 V/μs. A 2-wire serial interface that
operates at clock rates up to 400 kHz is used. This interface is
SMBus compatible at VDD < 3.6 V. Multiple devices can be
placed on the same bus.
The references for the four DACs are derived from one
reference pin. The outputs of all DACs can be updated
simultaneously using the software LDAC function.
The parts incorporate a power-on reset circuit, which ensures
that the DAC outputs power up to 0 V and remain there until a
valid write takes place to the device. There is also a software
clear function to reset all input and DAC registers to 0 V. The
parts contain a power-down feature that reduces the current
consumption of the devices to 200 nA @ 5 V (80 nA @ 3 V).
The low power consumption of these parts in normal operation
makes them ideally suited for portable battery-operated equip-
ment. The power consumption is 3 mW at 5 V, 1.5 mW at 3 V,
reducing to 1 μW in power-down mode.
1 Protected by U.S. Patent No. 5,969,657 and 5,684,481.
FUNCTIONAL BLOCK DIAGRAM
REF IN
GND
AD5305/AD5315/AD5325
SDA
SCL
A0
BUFFER
BUFFER
BUFFER
BUFFER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
VDD
LDAC
POWER-ON
RESET
INTERFACE
LOGIC
POWER-DOWN
LOGIC
STRING
DAC A
STRING
DAC B
STRING
DAC C
STRING
DAC D
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
VOUTD
VOUTC
VOUTB
VOUTA
Figure 1.


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