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AD5370 Datenblatt(PDF) 7 Page - Analog Devices

Teilenummer AD5370
Bauteilbeschribung  40-Channel,16-Bit, Serial Input, Voltage Output DAC
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Hersteller  AD [Analog Devices]
Direct Link  http://www.analog.com
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AD5370 Datenblatt(HTML) 7 Page - Analog Devices

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AD5370
Rev. 0 | Page 6 of 28
TIMING CHARACTERISTICS
DVCC = 2.5 V to 5.5 V; VDD = 9 V to 16.5 V; VSS = −16.5 V to −4.5 V; VREF = 3 V; AGND = DGND = SIGGND = 0 V; CL = 200 pF to GND;
RL = open circuit; gain (M), offset (C), and DAC offset registers at default values; all specifications TMIN to TMAX, unless otherwise noted.
Table 4. SPI Interface
Limit at TMIN, TMAX
Parameter 1, 2, 3
Min
Typ
Max
Unit
Description
t1
20
ns
SCLK cycle time
t2
8
ns
SCLK high time
t3
8
ns
SCLK low time
t4
11
ns
SYNC falling edge to SCLK falling edge setup time
t5
20
ns
Minimum SYNC high time
t6
10
ns
24th SCLK falling edge to SYNC rising edge
t7
5
ns
Data setup time
t8
5
ns
Data hold time
t94
42
ns
SYNC rising edge to BUSY falling edge
t10
1.5
μs
BUSY pulse width low (single-channel update); see Table 8
t11
600
ns
Single-channel update cycle time
t12
20
ns
SYNC rising edge to LDAC falling edge
t13
10
ns
LDAC pulse width low
t14
3
μs
BUSY rising edge to DAC output response time
t15
0
ns
BUSY rising edge to LDAC falling edge
t16
3
μs
LDAC falling edge to DAC output response time
t17
20
30
μs
DAC output settling time
t18
140
ns
CLR/RESET pulse activation time
t19
30
ns
RESET pulse width low
t20
400
μs
RESET time indicated by BUSY low
t21
270
ns
Minimum SYNC high time in readback mode
t225
25
ns
SCLK rising edge to SDO valid
t23
80
ns
RESET rising edge to BUSY falling edge
1 Guaranteed by design and characterization, not production tested.
2 All input signals are specified with tR = tF = 2 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.
3 See Figure 4 and Figure 5.
4 This is measured with the load circuit shown in Figure 2.
5 This is measured with the load circuit shown in Figure 3.
TIMING DIAGRAMS
TO
OUTPUT
PIN
CL
50pF
RL
2.2k
VOL
DVCC
VOH (MIN) – VOL (MAX)
2
200µA
IOL
200µA
IOH
TO OUTPUT
PIN
CL
50pF
Figure 2. Load Circuit for BUSY Timing Diagram
Figure 3. Load Circuit for SDO Timing Diagram


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