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8XC196KC20 Datenblatt(PDF) 3 Page - Intel Corporation

Teilenummer 8XC196KC20
Bauteilbeschribung  COMMERCIAL/EXPRESS CHMOS MICROCONTROLLER
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Hersteller  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

8XC196KC20 Datenblatt(HTML) 3 Page - Intel Corporation

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8XC196KC8XC196KC20
PROCESS INFORMATION
This device is manufactured on PX295 or PX299 a
CHMOS III process Additional process and reliabili-
ty information is available in Intel’s
Components
Quality and Reliability Handbook
Order Number
210997
270942 – 43
EXAMPLE
N87C196KC is 68-Lead PLCC OTPROM
16 MHz
For complete package dimensional data refer to the
Intel Packaging Handbook (Order Number 240800)
NOTE
1 EPROMs are available as One Time Programmable
(OTPROM) only
Figure 3 The 8XC196KC Family Nomenclature
Table 1 Thermal Characteristics
Package
ija
ijc
Type
PLCC
35 CW
13 CW
QFP
55 CW
16 CW
SQFP
TBD
TBD
All thermal impedance data is approximate for static air
conditions at 1W of power dissipation Values will change
depending on operation conditions and application See
the Intel
Packaging Handbook (order number 240800) for a
description of Intel’s thermal impedance test methodology
Table 2 8XC196KC Memory Map
Description
Address
External Memory or IO
0FFFFH
06000H
Internal ROMOTPROM or External
5FFFH
Memory (Determined by EA)
2080H
Reserved Must contain FFH
207FH
(Note 5)
205EH
PTS Vectors
205DH
2040H
Upper Interrupt Vectors
203FH
2030H
ROMOTPROM Security Key
202FH
2020H
Reserved Must contain FFH
201FH
(Note 5)
201AH
Reserved Must Contain 20H
2019H
(Note 5)
CCB
2018H
Reserved Must contain FFH
2017H
(Note 5)
2014H
Lower Interrupt Vectors
2013H
2000H
Port 3 and Port 4
1FFFH
1FFEH
External Memory
1FFDH
0200H
488 Bytes Register RAM (Note 1)
01FFH
0018H
CPU SFR’s (Notes 1 3 4)
0017H
0000H
NOTES
1 Code executed in locations 0000H to 01FFH will be
forced external
2 Reserved memory locations must contain 0FFH unless
noted
3 Reserved SFR bit locations must contain 0
4 Refer to 8XC196KC User’s manual for SFR descriptions
5 WARNING Reserved memory locations must not be
written or read The contents andor function of these lo-
cations may change with future revisions of the device
Therefore a program that relies on one or more of these
locations may not function properly
3


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