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AD7991 Datenblatt(PDF) 8 Page - Analog Devices |
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AD7991 Datenblatt(HTML) 8 Page - Analog Devices |
8 / 28 page AD7991/AD7995/AD7999 Rev. B | Page 8 of 28 A Version2 Y Version Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments LOGIC INPUTS (SDA, SCL) Input High Voltage, VINH 0.7 (VDD) 0.7 (VDD) V VDD = 2.7 V to 5.5 V 0.9 (VDD) V VDD = 2.35 V to 2.7 V Input Low Voltage, VINL 0.3 (VDD) 0.3 (VDD) V VDD = 2.7 V to 5.5 V 0.1 (VDD) V VDD = 2.35 V to 2.7 V Input Leakage Current, IIN ±1 ±1 μA VIN = 0 V or VDD Input Capacitance, CIN7 10 10 pF Input Hysteresis, VHYST 0.1 (VDD) 0.1 (VDD) V LOGIC OUTPUTS (OPEN DRAIN) Output Low Voltage, VOL 0.4 0.4 V ISINK = 3 mA 0.6 0.6 V ISINK = 6 mA Floating-State Leakage Current ±1 ±1 μA Floating-State Output Capacitance7 10 10 pF Output Coding Straight (natural) binary Straight (natural) binary THROUGHPUT RATE 18×(1/fSCL) 18×(1/fSCL) fSCL ≤ 1.7 MHz; see the Serial Interface section 17.5×(1/fSCL) + 2 μs 17.5×(1/fSCL) + 2 μs fSCL > 1.7 MHz; see the Serial Interface section POWER REQUIREMENTS3 VREF = VDD; for fSCL = 3.4 MHz, clock stretching is implemented VDD 2.7 5.5 2.7 5.5 V IDD Digital inputs = 0 V or VDD 0.09/0.25 mA VDD = 3.3 V/5.5 V, 400 kHz fSCL ADC Operating, Interface Active (Fully Operational) 0.25 0.25/0.8 mA VDD = 3.3 V/5.5 V, 3.4 MHz fSCL 0.07/0.16 mA VDD = 3.3 V/5.5 V, 400 kHz fSCL Power-Down, Interface Active8 0.26 0.26/0.85 mA VDD = 3.3 V/5.5 V, 3.4 MHz fSCL Power-Down , Interface Inactive8 1 1/1.6 μA VDD = 3.3 V/5.5 V Power Dissipation ADC Operating, Interface Active (Fully Operational) 0.83 0.3/1.38 0.83/4.4 mW mW VDD = 3.3 V/5.5 V, 400 kHz fSCL VDD = 3.3 V/5.5 V, 3.4 MHz fSCL 0.24/0.88 mW VDD = 3.3 V/5.5 V, 400 kHz fSCL Power-Down, Interface Active8 0.86 0.86/4.68 mW VDD = 3.3 V/5.5 V, 3.4 MHz fSCL Power-Down , Interface Inactive8 3.3 3.3/8.8 μW VDD = 3.3 V/5.5 V 1 Functional from VDD = 2.35 V. 2 A Version tested at VDD=3.3 V and fSCL= 3.4 MHz. Functionality tested at fSCL = 400 kHz. 3 Sample delay and bit trial delay enabled, t1 = t2 = 0.5/fSCL. 4 For fSCL up to 400 kHz, clock stretching is not implemented. Above fSCL = 400 kHz, clock stretching is implemented. 5 See the Terminology section. 6 For fSCL ≤ 1.7 MHz, clock stretching is not implemented; for fSCL > 1.7 MHz, clock stretching is implemented. 7 Guaranteed by initial characterization. 8 See the Reading from the AD7991/AD7995/AD7999 section. |
Ähnliche Teilenummer - AD7991_15 |
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Ähnliche Beschreibung - AD7991_15 |
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