AD9923A_15 datasheet(7/84 Pages) AD

Teilenummer	AD9923A

Bauteilbeschribung	CCD Signal Processor with V-Driver and Precision Timing Generator

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Hersteller	AD [Analog Devices]

Direct Link	http://www.analog.com

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AD9923A

Rev. A | Page 7 of 84

Parameter

Conditions/Comments

Symbol

Min

Typ

Max

Unit

SCK Falling Edge to SDATA Valid Hold

tDH

10

ns

SCK Falling Edge to SDATA Valid Read

tDV

10

ns

INHIBIT REGION FOR SHP AND SHD WITH

RESPECT TO H-CLOCK EDGE LOCATION

HxMASK = 0, HxRETIME = 0, HxPOLARITY = 0

tSHDINH

HxPOS − 9

HxPOS − 18

Edge

location

HxMASK = 0, HxRETIME = 0, HxPOLARITY = 1

tSHDINH

HxNEG − 9

HxNEG − 18

Edge

location

HxMASK = 0, HxRETIME = 1, HxPOLARITY = 0

tSHPINH

HxPOS − 7

HxPOS − 16

Edge

location

HxMASK = 0, HxRETIME = 1, HxPOLARITY = 1

tSHPINH

HxNEG − 7

HxNEG − 16

Edge

location

HxMASK = 1, HxRETIME = 0, HxPOLARITY = 0

tSHDINH

HxNEG − 9

HxNEG − 18

Edge

location

HxMASK = 1, HxRETIME = 0, HxPOLARITY = 1

tSHDINH

HxPOS − 9

HxPOS − 18

Edge

location

HxMASK = 1, HxRETIME = 1, HxPOLARITY = 0

tSHPINH

HxNEG − 7

HxNEG − 16

Edge

location

HxMASK = 1, HxRETIME = 1, HxPOLARITY = 1

tSHPINH

HxPOS − 7

HxPOS − 16

Edge

location

1 Parameter is programmable.

2 Minimum CLPOB pulse width is for functional operation only. Wider typical pulses are recommended to achieve good clamp performance.

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