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74ALVC_ALVCH16244 Datenblatt(PDF) 2 Page - NXP Semiconductors

Teilenummer 74ALVC_ALVCH16244
Bauteilbeschribung  2.5 V/3.3 V 16-bit buffer/line driver (3-state)
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Hersteller  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

74ALVC_ALVCH16244 Datenblatt(HTML) 2 Page - NXP Semiconductors

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2003 May 14
2
Philips Semiconductors
Product specification
2.5 V/3.3 V 16-bit buffer/line driver
(3-state)
74ALVC16244;
74ALVCH16244
FEATURES
• Wide supply voltage range from 1.2 to 3.6 V
• CMOS low power consumption
• MultiByte flow-through standard pin-out architecture
• Low inductance multiple VCC and GND pins for minimum
noise and ground bounce
• Direct interface with TTL levels
• Bus hold on data inputs (74ALVCH16244 only)
• Output drive capability 50 Ω transmission lines at 85 °C
• Current drive ±24 mA at 3.0 V
• Complies with JEDEC standard no. 8-1 A
• ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
DESCRIPTION
The 74ALVC16244; 74ALVCH16244 is a 16-bit
non-inverting buffer/line driver with 3-state outputs. The
device can be used as four 4-bit buffers, two 8-bit buffers
or one 16-bit buffer. The 3-state outputs are controlled by
the output enable inputs 1OE, 2OE, 3OE and 4OE. A
HIGH on nOE causes the outputs to assume a
high-impedance OFF-state.
The 74ALVCH16244 has active bus hold circuitry which is
provided to hold unused or floating data inputs at a valid
logic level. This feature eliminates the need for external
pull-up or pull-down resistors.
The 74ALVC16244 has 5 V tolerant inputs.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25 °C; tr =tf ≤ 2.5 ns
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD =CPD × VCC2 × fi × N+ Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
Σ(CL × VCC2 × fo) = sum of the outputs.
2. The condition is VI = GND to VCC.
SYMBOL
PARAMETERS
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
propagation delay nAn to nYn
VCC = 2.5 V; CL = 30 pF
1.9
ns
VCC = 3.3 V; CL = 50 pF
1.9
ns
CI
input capacitance
5.0
pF
CPD
power dissipation capacitance per buffer
notes 1 and 2
outputs enabled
25
pF
outputs disabled
4
pF


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