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74ALVCH162601 Datenblatt(PDF) 2 Page - NXP Semiconductors |
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74ALVCH162601 Datenblatt(HTML) 2 Page - NXP Semiconductors |
2 / 20 page 1999 Oct 14 2 Philips Semiconductors Product specification 18-bit universal bus transceiver with 30 Ω termination resistor; 3-state 74ALVCH162601 FEATURES • Complies with JEDEC standard no. 8-1A • CMOS low power consumption • Direct interface with TTL levels • MULTIBYTE™ flow-through standard pin-out architecture • Low inductance multiple VCC and ground pins for minimum noise and ground bounce • All data inputs have bus hold circuitry • Integrated 30 Ω termination resistors. DESCRIPTION The 74ALVCH162601 is an 18-bit universal transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA), and clock (CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CPAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A-bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CPAB. When OEAB is LOW, the outputs are active. When OEAB is HIGH, the outputs are in the high-impedance state. The clocks can be controlled with the clock-enable inputs (CEBA/CEAB). Data flow for B-to-A is similar to that of A-to-B but uses OEBA,LEBA and CPBA. To ensure the high-impedance state during power-down, OEBA and OEAB should be tied to VCC through a pull-up resistor, the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver. The 74ALVCH162601 is designed with 30 Ω series resistors in both HIGH or LOW output stage. Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level. QUICK REFERENCE DATA Ground = 0; Tamb =25 °C; tr =tf = 2.5 ns. Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD =CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; ∑ (CL × VCC2 × fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in Volts. 2. The condition is VI = GND to VCC. SYMBOL PARAMETER CONDITIONS TYPICAL UNIT tPHL/tPLH propagation delay An,Bn to Bn,An CL = 30 pF; VCC = 2.5 V 4.0 ns CL = 50 pF; VCC = 3.3 V 3.1 ns CI/O input/output capacitance 8.0 pF CI input capacitance 4.0 pF CPD power dissipation capacitance per latch notes 1 and 2 outputs enabled 21 pF outputs disabled 3 pF |
Ähnliche Teilenummer - 74ALVCH162601_15 |
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Ähnliche Beschreibung - 74ALVCH162601_15 |
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