Datenblatt-Suchmaschine für elektronische Bauteile |
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8T74S208A-01 Datenblatt(PDF) 7 Page - Integrated Device Technology |
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8T74S208A-01 Datenblatt(HTML) 7 Page - Integrated Device Technology |
7 / 19 page REVISION 1 06/15/15 7 2.5V DIFFERENTIAL LVDS CLOCK DIVIDER AND FANOUT BUFFER 8T74S208A-01 DATA SHEET AC Electrical Characteristics Table 5. AC Electrical Characteristics, VDD = VDDO = 2.5V ± 5%, TA = -40°C to 85°C 1 NOTE 1: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. Symbol Parameter Test Conditions Minimum Typical Maximum Units fREF Input Frequency IN, nIN 1GHz fSCL I2C Clock Frequency 400 kHz tJIT Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section, measured with FSEL[1:0] = 00 fREF =156.25, Integration Range: 12kHz – 20MHz 96 120 fs tPD Propagation Delay2 NOTE 2: Measured from the differential input crosspoint to the differential output crosspoint. IN, nIN to Qx, nQx FSEL[1:0] = 00 420 620 ps FSEL[1:0] = 01 580 800 ps FSEL[1:0] = 10 680 920 ps FSEL[1:0] = 11 780 1050 ps tsk(o) Output Skew3, 4 NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential crosspoint. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. 45 ps tsk(p) Pulse Skew FSEL[1:0] = 00 55 ps tsk(pp) Part-to-Part Skew4, 5, 6 NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential crosspoint. NOTE 6: Part-to-part skew specification does not guarantee divider synchronization among devices. 200 ps odc Output Duty Cycle7 NOTE 7: If FSEL[1:0] = 00 (divide-by-one), the output duty cycle will depend on the input duty cycle. FSEL[1:0] = 00 50 % FSEL[1:0] = 01 48 50 52 % FSEL[1:0] = 10 48 50 52 % FSEL[1:0] = 11 48 50 52 % tPDZ Output Enable and Disable Time8 NOTE 8: Measured from SDA rising edge of I2C stop command. Output Enable/ Disable State from/ to Active/ Inactive 1µs tR / tF Output Rise/ Fall Time 20% to 80% 155 230 ps 10% to 90% 245 350 ps |
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