9ZXL1550 datasheet(10/18 Pages) IDT

Teilenummer	9ZXL1550

Bauteilbeschribung	PLL or bypass mode

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Hersteller	IDT [Integrated Device Technology]

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15-O/P LP-HCSL DB1900Z DERIVATIVE FOR PCIE GEN1-2-3 AND QPI

10

REVISION D 06/16/15

9ZXL1550 DATASHEET

Driving LVDS

Clock Periods–Differential Outputs with Spread Spectrum Disabled

Clock Periods–Differential Outputs with Spread Spectrum Enabled

Driving LVDS inputs

Receiver has

termination

Receiver does

not have

termination

R7a, R7b

10K ohm

140 ohm

R8a, R8b

5.6K ohm

75 ohm

Cc

0.1 uF

Vcm

1.2 volts

Component

Value

Note

Rs

Device

Rs

Zo

Driving LVDS

Cc

R7a

R7b

R8a

R8b

3.3V

LVDS Clock

input

1 Clock

1us

0.1s

1us

1 Clock

-c2c jitter

AbsPer

Min

-SSC

Short-Term

Average

Min

- ppm

Long-Term

Average

Min

0 ppm

Period

Nominal

+ ppm

Long-Term

Average

Max

+SSC

Short-Term

Average

Max

+c2c jitter

AbsPer

Max

100.00

9.94900

9.99900

10.00000

10.00100

10.05100

ns

1,2,3

133.33

7.44925

7.49925

7.50000

7.50075

7.55075

ns

1,2,4

SSC OFF

Center

Freq.

MHz

DIF

Measurement Window

Units Notes

1 Clock

1us

0.1s

1us

1 Clock

-c2c jitter

AbsPer

Min

-SSC

Short-Term

Average

Min

- ppm

Long-Term

Average

Min

0 ppm

Period

Nominal

+ ppm

Long-Term

Average

Max

+SSC

Short-Term

Average

Max

+c2c jitter

AbsPer

Max

99.75

9.94906

9.99906

10.02406

10.02506

10.02607

10.05107

10.10107

ns

1,2,3

133.00

7.44930

7.49930

7.51805

7.51880

7.51955

7.53830

7.58830

ns

1,2,4

Notes:

1 Guaranteed by design and characterization, not 100% tested in production.

3 Driven by SRC output of main clock, 100 MHz PLL Mode or Bypass mode

4 Driven by CPU output of main clock, 133 MHz PLL Mode or Bypass mode

Measurement Window

Units

SSC ON

Center

Freq.

MHz

2 All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with CK420BQ/CK410B+

accuracy requirements (+/-100ppm). The 9ZXL1550 itself does not contribute to ppm error.

DIF

Notes

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