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8T49NS010 Datenblatt(PDF) 6 Page - Integrated Device Technology |
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8T49NS010 Datenblatt(HTML) 6 Page - Integrated Device Technology |
6 / 35 page 8T49NS010 DATA SHEET CLOCK SYNTHESIZER AND FANOUT BUFFER/DIVIDER 6 REVISION 1 11/19/14 Principles of Operation Depending on the input used, the 8T49NS010’s low phase noise integer-N PLL can multiply the reference to 2400MHz to 2500MHz. The device offers ten clock outputs (QCLK[9:0]/nQCLK[9:0]). Each output can be disabled individually through registers. With ÷2, ÷4, ÷8 and ÷16 values one can get output frequencies of 156.25MHz, 312.5MHz, 625MHz and 1250MHz when driven from a 25MHz input, for example. Table 4A to Table 4C show functions of the hardware pin settings. The input select pin REF_SEL will choose either XTAL input or CLK_IN input and this pin also set the pre-divider PRE to either x2 or ÷1. Feedback divider FB_SEL pin will set the feedback divider to either ÷50, ÷25. The VCO of this device is 2.5GHz. The feedback divider should be properly set to assure the PLL lock for VCO=2.5GHz. N1 and N0 are pins for output frequency divider setting. Table 4D provide some examples of setting output to 156.25MHz. N1 and N0 can be set for other output frequencies. Additional divider values are available through registers that can be programmed with I2C interface. Table 4C lists the frequencies available with select pins on the device, while Table 4E lists all available divider configurations via I2C. The 8T49NS010 operates over the industrial temperature range of -40°C to +85°C. The outputs are compatible with LVPECL-type logic levels, described as FORMAT #1 or FORMAT #2 (see Termination for QCLKn Outputs) and the DC characteristics for these two formats in the DC Electrical Characteristics (Table 6D and Table 6E). Table 4C, below, shows an example using a 2500MHz VCO frequency input with the selected output dividers shown, resulting in the listed output frequencies. The output divider N can also be set via internal registers. The configuration and re-configuration of any of the output dividers requires an I2C write sequence. Each QCLK output can be individually disabled through an I2C command. FB_SEL Feedback Divider 0 (Default) ÷50 1 ÷25 Table 4C. Hardware Pins N1 and N0 Output Frequency Divider Setting Table 4D. Hardware Pin Setting Examples Reference Clock Inputs The 8T49NS010 features one differential reference clock input (CLK_IN, nCLK_IN) and a crystal input. This input can be configured to operate in full differential mode (LVDS or LVPECL) or single-ended 3.3V CMOS mode. (The input signal frequency is divided down through a prescaler function (PV).) The reference input divider (PV) provides division ratios as shown in Table 4F. This divider setting may be adjusted via the PV bit in the Reference Control Register. Table 4F. Available Pre-Divider Settings (PV), I2C Only Table 4A. REF_SEL Input Pin Setting REF_SEL INPUT ÷PRE 0 (Default) XTAL_IN X2 1 CLK_IN ÷1 Table 4B. FBSEL Feedback divider Pin Setting N[1:0] Output Divider N Output Frequency (FVCO = 2500MHz) 00 ÷2 1250MHz 01 ÷4 625MHz 10 ÷8 312.5MHz 11 (Default) ÷16 156.25MHz Input (MHz) REF_SEL FB_SEL N[1:0] Output (VCO=2500MHz) Comments XTAL_IN=25 0, [PRE=x2] 0[÷50] 11[÷16] 156.25MHz Default XTAL_IN=50 0, [PRE=x2] 1[÷25] 11[÷16] 156.25MHz Recommended CLK_IN=50 1, [PRE=÷1] 0[÷50] 11[÷16] 156.25MHz CLK_IN=100 1, [PRE=÷1] 1[÷25] 11[÷16] 156.25MHz Table 4E. Output Frequency Divider Settings, I2C Only N[3:0] Divider Value 0000 ÷1 0001 ÷2 0010 ÷3 0011 ÷4 0100 ÷5 0101 ÷6 0110 ÷8 0111 ÷10 1000 ÷12 1001 ÷16 1010 ÷20 1011 ÷24 Register Bits PDIV[1:0] PV Divider Settings 00 x2 01 ÷1 10 ÷2 11 ÷4 |
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