M1008

Preliminary

CMOS IC

UNISONICTECHNOLOGIESCO.,LTD

6 of 11

www.unisonic.com.tw

QW-R502-434.a

FUNCTIONAL DESCRIPTION

Offset Error

At a level of 1/2 LSB above the nominal zero scale voltage, the first ADC code transition should come. The

offset error is defined as the deviation between the actual first code transition level with the ideal level.

Gain Error

At a level of 1/2 LSB below the nominal full-scale voltage, the last code transition should come. Gain error is

defined as the deviation of the actual difference between the first and the last code transitions and the ideal

difference between the first and the last code transitions.

Internal Register Descriptions

Address

Data Bits

Register

Name

A2

A1

A0

D8

D7

D6

D5

D4

D3

D2

D1

D0

Configuration

0

0

0

0

0

1

3-CH

CDS

on

Clamp

Voltage

Enable

Power Down

Output

Delay

1 byte out

MUX

0

0

1

0

RGB/

BGR

Red

Green

Blue

Delay

enable

CDSCLK1

Delay

CDSCLK

2 Delay

ADCCLK

Delay

Red PGA

0

1

0

0

0

0

MSB

LSB

Green PGA

0

1

1

0

0

0

MSB

LSB

Blue PGA

1

0

0

0

0

0

MSB

LSB

Red Offset

1

0

1

MSB

LSB

Green Offset

1

1

0

MSB

LSB

Blue Offset

1

1

1

MSB

LSB

Internal Register Map

Configuration Register

The configuration register sets the M1008’s operating mode and bias levels. Bits D6 should always hold high.

Bit D5 configures the M1008 for the 3-channel(high) operation mode. Bit D4 will be set high to implement the CDS

mode operation, and be set low to implement the SHA mode operation.

Bit D3 controls the dc bias level of the M1008’s input clamp. This bit should hold high for the 4V clamp bias,

unless a CCD with a reset feed through transient exceeding 2V is applied. The clamp voltage is 3V with this bit low.

Bit D2 controls the power-down mode. With bit D2 high, the M1008 will come to a very low power “sleep” mode,

in which all register contents are retained. Bit D1 is set high for the digital output (D0~D7) delay 2ns. Bit D0

configures the output mode of the M1008. Setting the bit high can implement a single byte output mode in which only

one byte of the 16b ADC is output. Inversely, the 16b ADC output is multiplexed into two bytes.

D8

D7

D6

D5

D4

D3

D2

D1

D0

3-Channels

CDS Operation

Clamp Bias

Power-Down

Output Delay

High Byte Out

1=on (Note)

1=CDS mode

(Note)

1=4V (Note)

1=on

1=on

1=on

0

0

1

0=off

0=SHA mode

0=3V

0=off (Note)

0=off (Note)

0=off

Configuration Register Settings

Note: Power-on default value

MUX Register

The sampling channel order and 2-channel mode configuration in the M1008 are both controlled by the MUX

register. Bits D8 should hold low. Bit D7 goes into effect in the 3-channel mode or the 2-channel mode of operation.

Setting it high will sequence the MUX to sample the red channel first, then the green channel, and the last blue

channel. In the 3-channel mode, the CDSCLK2 rising edge always resets the MUX to sample the red channel first

(see timing diagrams). When bit D7 is set low, the channel order is reversed to blue first, green second, and red third,

the CDSCLK2 rising edge will always reset the MUX to sample the blue channel first. Bits D6, D5, and D4 go into

effect when operating in 1 or 2-channel mode. Bit D6 is set high to sample the red channel. Bit D5 is set high to

sample the green channel. Bit D4 is set high to sample the blue channel. The MUX remains stationary during

is selected by bit D7. Bits D0~D3 are applied to controlling CDSCLK1, CDSCLK2 and ADCCLK internal delay.