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GS1672 Datenblatt(PDF) 11 Page - Gennum Corporation

Teilenummer GS1672
Bauteilbeschribung  Integrated Cable Driver
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Hersteller  GENNUM [Gennum Corporation]
Direct Link  http://www.gennum.com
Logo GENNUM - Gennum Corporation

GS1672 Datenblatt(HTML) 11 Page - Gennum Corporation

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GS1672 HD/SD-SDI Serializer with Complete SMPTE
Audio & Video Support
Data Sheet
53623 - 6
July 2011
11 of 116
A4
H/HSYNCSynch-
ronous
with
PCLK
Input
PARALLEL DATA TIMING.
Signal levels are LVCMOS / LVTTL compatible.
TIM_861 is LOW:
The H signal is used to indicate the portion of the video line
containing active video data, when DETECT_TRS is set LOW.
Active Line Blanking
The H signal should be LOW for the active portion of the video line.
The signal goes LOW at the first active pixel of the line, and then
goes HIGH after the last active pixel of the line.
The H signal should be set HIGH for the entire horizontal blanking
period, including both EAV and SAV TRS words, and LOW otherwise.
TRS Based Blanking (H_CONFIG = 1h)
The H signal should be set HIGH for the entire horizontal blanking
period as indicated by the H bit in the received TRS ID words, and
LOW otherwise.
TIM_861 = HIGH:
The HSYNC signal indicates horizontal timing. See Section 4.3.
When DETECT_TRS is HIGH, this pin is ignored at all times.
If DETECT_TRS is set HIGH and TIM_861 is set HIGH, the DETECT_TRS
feature will take priority.
A5, E1, G10,
K8
CORE_VDD
Input Power
Power supply connection for digital core logic. Connect to 1.2V DC
digital.
A6, B6
PLL_VDD
Input Power
Power supply pin for PLL. Connect to 1.2V DC analog.
A7
LF
Analog
Output
Loop Filter component connection.
A8
VBG
Output
Bandgap voltage filter connection.
A9, D6, D7,
D8, F4
RSV
These pins are reserved and should be left unconnected.
A10
A_VDD
Input Power
VDD for sensitive analog circuitry. Connect to 3.3VDC analog.
B4
PCLK
Input
PARALLEL DATA BUS CLOCK.
Signal levels are LVCMOS / LVTTL compatible.
HD 20-bit modePCLK @ 74.25MHz
HD 10-bit modePCLK @ 148.5MHz
SD 20-bit modePCLK @ 13.5MHz
SD 10-bit modePCLK @ 27MHz
DVB-ASI modePCLK @ 27MHz
B5, C5, E2,
E5, E6, F5,
F6, G9
CORE_GND
Input Power
GND connection for digital logic. Connect to digital GND.
B7
VCO_VDD
Input Powe
r
Power pin for the VCO. Connect to a 1.2V±5% analog supply,
followed by a RC filter (see Typical Application Circuit on page 111).
A 105
Ω 1% resistor must be used in the RC filter circuit. VCO_VDD is
nominally 0.7V.
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
Description


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