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ISL23328TFVZ-TK Datenblatt(PDF) 8 Page - Intersil Corporation |
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ISL23328TFVZ-TK Datenblatt(HTML) 8 Page - Intersil Corporation |
8 / 20 page ISL23328 8 FN7902.1 September 29, 2015 tHD:STA START Condition Hold Time From SDA falling edge crossing 30% of VLOGIC to SCL falling edge crossing 70% of VLOGIC 600 ns tSU:DAT Input Data Set-up Time From SDA exiting the 30% to 70% of VLOGIC window, to SCL rising edge crossing 30% of VLOGIC 100 ns tHD:DAT Input Data Hold Time From SCL falling edge crossing 70% of VLOGIC to SDA entering the 30% to 70% of VLOGIC window 0ns tSU:STO STOP Condition Set-up Time From SCL rising edge crossing 70% of VLOGIC, to SDA rising edge crossing 30% of VLOGIC 600 ns tHD:STO STOP Condition Hold Time for Read or Write From SDA rising edge to SCL falling edge; both crossing 70% of VLOGIC 1300 ns tDH Output Data Hold Time From SCL falling edge crossing 30% of VLOGIC, until SDA enters the 30% to 70% of VLOGIC window. IOL =3mA, VLOGIC > 2V. IOL = 0.5mA, VLOGIC < 2V 0ns tR SDA and SCL Rise Time From 30% to 70% of VLOGIC 20 + 0.1 x Cb 250 ns tF SDA and SCL Fall Time From 70% to 30% of VLOGIC 20 + 0.1 x Cb 250 ns Cb Capacitive Loading of SDA or SCL Total on-chip and off-chip 10 400 pF tSU:A A2, A1, A0 Setup Time Before START condition 600 ns tHD:A A2, A1, A0 Hold Time After STOP condition 600 ns NOTES: 7. Typical values are for TA = +25°C and 3.3V supply voltages. 8. LSB = [V(RW)127 – V(RW)0]/127. V(RW)127 and V(RW)0 are V(RW) for the DCP register set to 7F hex and 00 hex respectively. LSB is the incremental voltage when changing from one tap to an adjacent tap. 9. ZS error = V(RW)0/LSB. 10. FS error = [V(RW)127 – VCC]/LSB. 11. DNL = [V(RW)i – V(RW)i-1]/LSB-1, for i = 1 to 127. i is the DCP register setting. 12. INL = [V(RW)i – i • LSB – V(RW)0]/LSB for i = 1 to 127 13. For i = 8 to 127decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper voltage and Min( ) is the minimum value of the wiper voltage over the temperature range. 14. MI = |RW127 – RW0|/127. MI is a minimum increment. RW127 and RW0 are the measured resistances for the DCP register set to 7F hex and 00 hex respectively. 15. Roffset = RW0/MI, when measuring between RW and RL. Roffset = RW127/MI, when measuring between RW and RH. 16. RDNL = (RWi – RWi-1)/MI -1, for i = 8 to 127. 17. RINL = [RWi – (MI • i) – RW0]/MI, for i = 8 to 127. 18. for i = 8 to 127, T = -40°C to +125°C. Max( ) is the maximum value of the resistance and Min( ) is the minimum value of the resistance over the temperature range. 19. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 20. It is preferable to ramp up both the VLOGIC and the VCC supplies at the same time. If this is not possible, it is recommended to ramp-up the VLOGIC first followed by the VCC. 21. VMATCH = [V(RWx)i - V(RWy)i]/LSB, for i = 1 to 127, x = 0 to 1 and y = 0 to 1. 22. RMATCH = (RWi,x - RWi,y)/MI, for i = 1 to 127, x = 0 to 1 and y = 0 to 1. Serial Interface Specification For SCL, SDA, A0, A1, A2 unless otherwise noted. (Continued) SYMBOL PARAMETER TEST CONDITIONS MIN (Note 19) TYP (Note 7) MAX (Note 19) UNITS TCV Max V RW i Min V RW i – VRWi +25°C ------------------------------------------------------------------------------ 106 +165°C --------------------- = TCR Max Ri Min Ri – Ri +25°C ------------------------------------------------------- 10 6 +165°C --------------------- = |
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