ISL23315

7

FN7778.2

August 12, 2015

Wiper Response Time

W option; SCL rising edge of the

acknowledge bit after data byte to wiper

new position from 10% to 90% of the

final value.

0.4

µs

U option; SCL rising edge of the

acknowledge bit after data byte to wiper

new position from 10% to 90% of the

final value.

1.5

µs

T option; SCL rising edge of the

acknowledge bit after data byte to wiper

new position from 10% to 90% of the

final value.

3.5

µs

Leakage Current, at Pins A0, A1, SDA,

SCL

-0.4

<0.1

0.4

µA

tShdnRec DCP Recall Time from Shutdown Mode

SCL rising edge of the acknowledge bit

after ACR data byte to wiper recalled

position and RH connection

1.5

µs

Ramp

(Note 21)

Ramp monotonic at any level

0.01

50

V/ms

stated. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued)

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

(Note 20)

TYP

(Note 8)

MAX

(Note 20)

UNITS

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

(Note 20)

TYP

(Note 8)

MAX

(Note 20)

UNITS

Input LOW Voltage

-0.3

V

Input HIGH Voltage

V

Hysteresis

SDA and SCL Input Buffer

Hysteresis

V

SDA Output Buffer LOW Voltage

0

0.4

V

V

SDA, SCL Pin Capacitance

10

pF

SCL Frequency

400

kHz

Pulse Width Suppression Time at

SDA and SCL Inputs

Any pulse narrower than the

max spec is suppressed

50

ns

SCL Falling Edge to SDA Output

Data Valid

SCL falling edge crossing 30%

900

ns

Time the Bus Must be Free Before

the Start of a New Transmission

during a STOP condition, to

during the following START

condition

1300

ns

Clock LOW Time

Measured at the 30% of

1300

ns

Clock HIGH Time

Measured at the 70% of

600

ns

START Condition Set-up Time

SCL rising edge to SDA falling

edge; both crossing 70% of

600

ns