Datenblatt-Suchmaschine für elektronische Bauteile |
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ISL267450IUZ Datenblatt(PDF) 11 Page - Intersil Corporation |
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ISL267450IUZ Datenblatt(HTML) 11 Page - Intersil Corporation |
11 / 19 page ISL267450 11 FN8341.0 August 10, 2012 Functional Description The ISL267450 is based on a successive approximation register (SAR) architecture utilizing capacitive charge redistribution digital-to-analog converters (DACs). Figure 19 shows a simplified representation of the converter. During the acquisition phase (ACQ), the differential input is stored on the sampling capacitors (CS). The comparator is in a balanced state since the switch across its inputs is closed. The signal is fully acquired after tACQ has elapsed, and the switches then transition to the conversion phase (CONV) so the stored voltage may be converted to digital format. The comparator will become unbalanced when the differential switch opens and the input switches transition (assuming that the stored voltage is not exactly at mid-scale). The comparator output reflects whether the stored voltage is above or below mid-scale, which sets the value of the MSB. The SAR logic then forces the capacitive DACs to adjust up or down by one quarter of full-scale by switching in binarily weighted capacitors. Again the comparator output reflects whether the stored voltage is above or below the new value, setting the value of the next lowest bit. This process repeats until all 12 bits have been resolved. FIGURE 15. HISTOGRAM OF THE OUTPUT CODES WITH A DC INPUT FOR VDD = 5V FIGURE 16. HISTOGRAM OF THE OUTPUT CODES WITH A DC INPUT FOR VDD = 3V FIGURE 17. CHANGE IN ENOB vs VREF FOR VDD = 5V AND 3.3V FIGURE 18. CMRR vs INPUT FREQUENCY FOR VDD = 5V AND 3V Typical Performance Characteristics (Continued) 0 10000 20000 30000 40000 50000 60000 70000 2044 2045 2046 2047 2048 2049 2050 OUTPUT CODE 0 10000 20000 30000 40000 50000 60000 70000 2044 2045 2046 2047 2048 2049 2050 OUTPUT CODE 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 VREF (V) 3.3V VDD 5V VDD 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 -110 -100 -90 -80 -70 -60 -50 -40 10 100 1k 10k FREQUENCY (kHz) FIGURE 19. SAR ADC ARCHITECTURAL BLOCK DIAGRAM VIN+ VIN- VREF ACQ CONV ACQ ACQ CONV CONV SAR LOGIC CS CS |
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