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SM39R4051 Datenblatt(PDF) 6 Page - SyncMOS Technologies,Inc |
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SM39R4051 Datenblatt(HTML) 6 Page - SyncMOS Technologies,Inc |
6 / 47 page SM39R4051/SM39R2051 8-Bit Micro-controller 4KB/2KB with ISP Flash & 256B RAM embedded Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M055 6 Ver.E SM39R4051 09/2011 Pin Description 20L PDIP/SOP Symbol I/O Description 1 RESET(default)/ P3.6 I/O Reset pin(default) & Bit 6 of port 3 2 P3.0/RXD/#INT0/T0 I/O Bit 0 of port 3 & Serial interface channel receive/transmit data & (External interrupt 0 or Timer 0 external input) 3 P3.1/TXD/#INT1/T1 I/O Bit 1 of port 3 & Serial interface channel transmit data or receive clock in mode 0 & (External interrupt 1 or Timer 1 external input) 4 XTAL2/P4.0 I/O Crystal output & Bit 0 of port 4 5 XTAL1/P4.1 I/O Crystal input & Bit 1 of port 4 6 P3.2/#INT0 I/O Bit 2 of port 3 & External interrupt 0 7 P3.3/#INT1 I/O Bit 3 of port 3 & External interrupt 1 8 P3.4/T0 I/O Bit 4 of port 3 & Timer 0 external input 9 P3.5/T1 I/O Bit 5 of port 3 & Timer 1 external input 10 VSS I Power supply 11 P3.7 I/O Bit 7 of port 3 12 P1.0/SDA I/O Bit 0 of port 1 & On-Chip Instrumentation Command and data I/O pin synchronous to OCI_SCL in ICE and ICP functions 13 P1.1/SCL I/O Bit 1 of port 1 & On-Chip Instrumentation Clock I/O pin of ICE and ICP functions 14 P1.2/T0 I/O Bit 2 of port 1 & Timer 0 external input 15 P1.3/T1 I/O Bit 3 of port 1 & Timer 1 external input 16 P1.4/#INT0/T0/RESET I/O Bit 4 of port 1 & (External interrupt 0 or Timer 0 external input or RESET) 17 P1.5/#INT1/T1 I/O Bit 5 of port 1 & (External interrupt 1 or Timer 1 external input) 18 P1.6 I/O Bit 6 of port 1 19 P1.7 I/O Bit 7 of port 1 20 VDD I Power supply The Special Function Pin Can configured as below Table (Can be Select By SFR): Signal Default Option1 Option2 Option3 #INT0 6(P3.2) 2(P3.0) 15(P1.3) 16(P1.4) #INT1 7(P3.3) 3(P3.1) 14(P1.2) 17(P1.5) T0 8(P3.4) 14(P1.2) 16(P1.4) 2(P3.0) T1 9(P3.5) 15(P1.3) 17(P1.5) 3(P3.1) The RESET Pin Can configured as below Table (Can be Select By ICP or ISP ): Signal Default Option1 RESET 1 16 The RESET Pin Can Be configured as I/O port P3.6,when user use on-chip hardware RESET mechanism。 The XTAL2 can be configured as I/O port P4.0 by ICP or in ISP mode.,when user use Oscillator (XTAL1 as clock input) or on-chip RC Oscillator is set to main system clock source。 The XTAL1 can be configured as I/O port P4.1 by ICP or in ISP mode,when user use on-chip RC Oscillator is set to main system clock source。 |
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