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ML4802CS Datenblatt(PDF) 11 Page - Micro Linear Corporation |
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ML4802CS Datenblatt(HTML) 11 Page - Micro Linear Corporation |
11 / 15 page ML4802 11 August 2000 Datasheet PWM SECTION Pulse Width Modulator The PWM section of the ML4802 is straightforward, but there are several points which should be noted. Foremost among these is its inherent synchronization to the PFC section of the device, from which it also derives its basic timing (at twice the PFC frequency in the ML4802). The PWM is primarily intended for current-mode operation. In current-mode applications, the PWM ramp (RAMP 2) is usually derived directly from a current sensing resistor in the primary of the output stage, and is thereby representative of the current flowing in the converter’s output stage. DC ILIMIT, which provides cycle-by-cycle current limiting, is internally connected to RAMP 2. No voltage error amplifier is included in the PWM stage of the ML4802, as this function is generally performed on the output side of the PWM’s isolation boundary. To facilitate the design of optocoupler feedback circuitry, an offset has been built into the PWM’s RAMP 2 input which allows VDC to command a zero percent duty cycle for input voltages below 1.25V. VIN OK Comparator The VIN OK comparator monitors the DC output of the PFC and inhibits the PWM if this voltage on VFB is less than its nominal 2.5V. Once this voltage reaches 2.5V, which corresponds to the PFC output capacitor being charged to its rated boost voltage, the soft-start commences. PWM Control (RAMP 2) RAMP 2 is the sampling point for a voltage representing the current in the primary of the PWM’s output transformer, derived from a current sensing resistor. PWM Current Limit The DC ILIMIT pin is a cycle-by-cycle current limiter for the PWM section. It is connected internally to the PWM control pin. Should the input voltage at this pin ever exceed 1.5V, the output of the PWM will be disabled until the output flip-flop is reset by the clock pulse at the start of the next PWM power cycle. Soft Start Start-up of the PWM is controlled by the selection of the external capacitor at SS. A current source of 25µA supplies the charging current for the capacitor, and start- up of the PWM begins at 1.25V. Start-up delay can be programmed by the following equation: where CSS is the required soft start capacitance, and tDELAY is the desired start-up delay. FUNCTIONAL DESCRIPTION (Continued) It is important that the time constant of the PWM soft-start allow the PFC time to generate sufficient output power for the PWM section. The PWM start-up delay should be at least 5ms. Solving for the minimum value of CSS: Generating VCC The ML4802 is a voltage-fed part. It requires an external 15V±10% (or better) Zener shunt voltage regulator, or other controlled supply, to maintain the voltage supplied to the part at 15V nominal. This allows a low power dissipation while at the same time delivering 13V nominal of gate drive at the PWM OUT and PFC OUT outputs. LEADING/TRAILING MODULATION Conventional Pulse Width Modulation (PWM) techniques employ trailing edge modulation in which the switch will turn on right after the trailing edge of the system clock. The error amplifier output voltage is then compared with the modulating ramp. When the modulating ramp reaches the level of the error amplifier output voltage, the switch will be turned OFF. When the switch is ON, the inductor current will ramp up. The effective duty cycle of the trailing edge modulation is determined during the ON of the switch. Figure 5 shows a typical trailing edge control scheme. RAMP VEAO TIME VSW1 TIME REF EA – + – + OSC DFF R D Q Q CLK U1 RAMP CLK U4 U3 C1 RL I4 SW2 SW1 + DC I1 I2 I3 VIN L1 U2 Figure 5. Typical Trailing Edge Control Scheme CSS tDELAY 25 A 1.25V = m CSS 5ms 25 A 1.25V nF = @ m 200 |
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