MMSF1310

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4

POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted

by recognizing that the power MOSFET is charge

controlled. The lengths of various switching intervals (

∆t)

are determined by how fast the FET input capacitance can

be charged by current from the generator.

The published capacitance data is difficult to use for

calculating rise and fall because drain−gate capacitance

varies greatly with applied voltage. Accordingly, gate

charge data is used. In most cases, a satisfactory estimate of

rudimentary analysis of the drive circuit so that

During the rise and fall time interval when switching a

times may be approximated by the following:

where

During the turn−on and turn−off delay times, gate current is

not constant. The simplest calculation uses appropriate

values from the capacitance curves in a standard equation for

voltage change in an RC network. The equations are:

a voltage corresponding to the off−state condition when

At high switching speeds, parasitic circuit elements

complicate the analysis. The inductance of the MOSFET

source lead, inside the package and in the circuit wiring

which is common to both the drain and gate current paths,

produces a voltage at the source which reduces the gate drive

current. The voltage is determined by Ldi/dt, but since di/dt

is a function of drain current, the mathematical solution is

complex.

The

MOSFET

output

capacitance

also

complicates the mathematics. And finally, MOSFETs have

finite internal gate resistance which effectively adds to the

resistance of the driving source, but the internal resistance

is difficult to measure and, consequently, is not specified.

The resistive switching time variation versus gate resistance

(Figure 8) shows how typical switching performance is

affected by the parasitic circuit elements. If the parasitics

were not present, the slope of the curves would maintain a

value of unity regardless of the switching speed. The circuit

used to obtain the data is constructed to minimize common

inductance in the drain and gate circuit loops and is believed

readily achievable with board mounted components. Most

power electronic loads are inductive; the data in the figure

is taken with a resistive load, which approximates an

optimally snubbed inductive load. Power MOSFETs may be

safely operated into an inductive load; however, snubbing

reduces switching losses.

Figure 7. Capacitance Variation

−10

0

5

10

−5

4000

15

30

0

1000

20

25

2000

3000