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MC74VHCT50AD Datenblatt(PDF) 1 Page - ON Semiconductor

Teilenummer MC74VHCT50AD
Bauteilbeschribung  Noninverting Buffer / CMOS Logic Level Shifter with LSTTL-Compatible Inputs
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© Semiconductor Components Industries, LLC, 2001
July, 2001– Rev. 3
1
Publication Order Number:
MC74VHCT50A/D
MC74VHCT50A
Noninverting Buffer /
CMOS Logic Level Shifter
with LSTTL–Compatible Inputs
The MC74VHCT50A is a hex noninverting buffer fabricated with
silicon gate CMOS technology. It achieves high speed operation
similar to equivalent Bipolar Schottky TTL while maintaining CMOS
low power dissipation.
The internal circuit is composed of three stages, including a buffered
output which provides high noise immunity and stable output.
The device input is compatible with TTL–type input thresholds and
the output has a full 5 V CMOS level output swing. The input
protection circuitry on this device allows overvoltage tolerance on the
input, allowing the device to be used as a logic–level translator from
3.0 V CMOS logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic
to 3.0 V CMOS Logic while operating at the high–voltage power
supply.
The MC74VHCT50A input structure provides protection when
voltages up to 7 V are applied, regardless of the supply voltage. This
allows the MC74VHCT50A to be used to interface 5 V circuits to 3 V
circuits. The output structures also provide protection when
VCC = 0 V. These input and output structures help prevent device
destruction caused by supply voltage – input/output voltage mismatch,
battery backup, hot insertion, etc.
High Speed: t
PD = 3.5 ns (Typ) at VCC = 5 V
Low Power Dissipation: I
CC = 2 µA (Max) at TA = 25°C
TTL–Compatible Inputs: V
IL = 0.8 V; VIH = 2.0 V
CMOS–Compatible Outputs: V
OH > 0.8 VCC; VOL < 0.1 VCC @Load
Power Down Protection Provided on Inputs and Outputs
LOGIC DIAGRAM
Y1
A1
A2
A3
A4
A5
A6
Y2
Y3
Y4
Y5
Y6
1
3
5
9
11
13
2
4
6
8
10
12
Y = A
A1
Y1
1
A2
Y2
1
A3
Y3
1
A4
Y4
1
A5
Y5
1
A6
Y6
1
LOGIC SYMBOL
14–LEAD SOIC
D SUFFIX
CASE 751A
http://onsemi.com
14–LEAD TSSOP
DT SUFFIX
CASE 948G
PIN CONNECTION AND
MARKING DIAGRAM (Top View)
Device
Package
Shipping
ORDERING INFORMATION
MC74VHCT50AD
SOIC
55 Units/Rail
MC74VHCT50ADT
TSSOP
96 Units/Rail
13
14
12
11
10
9
8
2
1
34567
VCC
A6
Y6
A5
Y5
A4
Y4
A1
Y1
A2
Y2
A3
Y3
GND
14–LEAD SOIC EIAJ
M SUFFIX
CASE 965
MC74VHCT50AM
SOIC EIAJ
50 Units/Rail
FUNCTION TABLE
L
H
A Input
Y Output
L
H
For detailed package marking information, see the Marking
Diagram section on page 4 of this data sheet.


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