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TMP275AQDRQ1 Datenblatt(PDF) 11 Page - Texas Instruments

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Teilenummer TMP275AQDRQ1
Bauteilbeschribung  Automotive Grade Temperature Sensor
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Hersteller  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
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TMP275-Q1
www.ti.com
SBOS760A – NOVEMBER 2015 – REVISED JANUARY 2016
Product Folder Links: TMP275-Q1
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Copyright © 2015–2016, Texas Instruments Incorporated
7.3.4.3 SMBus Alert Function
The TMP275-Q1 supports the SMBus alert function. When the TMP275-Q1 is operating in interrupt mode (TM =
1), the ALERT pin of the TMP275-Q1 can be connected as an SMBus alert signal. When a master senses that
an Alert condition is present on the ALERT line, the master sends an SMBus Alert command (00011001) on the
bus. If the ALERT pin of the TMP275-Q1 is active, the device acknowledges the SMBus Alert command and
responds by returning its slave address on the SDA line. The eighth bit (LSB) of the slave address byte indicates
if the temperature exceeding THIGH or falling below TLOW caused the Alert condition. This bit is high if the
temperature is greater than or equal to THIGH. This bit is low if the temperature is less than TLOW; see Figure 10
for details of this sequence.
If multiple devices on the bus respond to the SMBus Alert command, arbitration during the slave address portion
of the SMBus Alert command determines which device clears its Alert status. If the TMP275-Q1 wins the
arbitration, its ALERT pin becomes inactive at the completion of the SMBus Alert command. If the TMP275-Q1
loses the arbitration, its ALERT pin remains active.
7.3.4.4 General Call
The TMP275-Q1 responds to a two-wire, general-call address (0000000) if the eighth bit is 0. The device
acknowledges the general-call address and responds to commands in the second byte. If the second byte is
00000100, the TMP275-Q1 latches the status of its address pins but does not reset. If the second byte is
00000110, the TMP275-Q1 latches the status of its address pins and resets its internal registers to their power-
up values.
7.3.4.5 High-Speed Mode
For the two-wire bus to operate at frequencies above 400 kHz, the master device must issue an Hs-mode master
code (00001XXX) as the first byte after a START condition to switch the bus to high-speed operation. The
TMP1275 device does not acknowledge this byte, but does switch its input filters on SDA and SCL and its output
filters on SDA to operate in Hs-mode, thus allowing transfers at up to 2.38 MHz. After the Hs-mode master code
is issued, the master transmits a two-wire slave address to initiate a data transfer operation. The bus continues
to operate in Hs-mode until a STOP condition occurs on the bus. Upon receiving the STOP condition, the
TMP275-Q1 switches the input and output filter back to fast-mode operation.
7.3.4.6 Time-Out Function
The TMP275-Q1 resets the serial interface if either SCL or SDA is held low for 54 ms (typical) between a START
and STOP condition. The TMP275-Q1 releases the bus if it is pulled low and waits for a START condition. To
avoid activating the time-out function, a communication speed of at least 1 kHz must be maintained for the SCL
operating frequency.
7.3.5 Timing Diagrams
The TMP275-Q1 is two-wire, SMBus, and I2C interface compatible. Figure 7 to Figure 10 describe the various
operations on the TMP275-Q1. The following list provides bus definitions. Parameters for Figure 7 are defined in
the Timing Requirements table.
Bus Idle: Both the SDA and SCL lines remain high.
Start Data Transfer: A change in the state of the SDA line, from high to low when the SCL line is high defines a
START condition. Each data transfer is initiated with a START condition.
Stop Data Transfer: A change in the state of the SDA line from low to high when the SCL line is high defines a
STOP condition. Each data transfer is terminated with a repeated START or STOP condition.
Data Transfer: The number of data bytes transferred between a START and a STOP condition is not limited and
is determined by the master device. The receiver acknowledges the transfer of data.
Acknowledge: Each receiving device, when addressed, is obliged to generate an Acknowledge bit. A device
that acknowledges must pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA
line is stable low during the high period of the Acknowledge clock pulse. Setup and hold times must be taken into
account. On a master receive, the termination of the data transfer can be signaled by the master generating a
Not-Acknowledge bit on the last byte that is transmitted by the slave.


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