Datenblatt-Suchmaschine für elektronische Bauteile |
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TPA3111D1-Q1 Datenblatt(PDF) 3 Page - Texas Instruments |
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TPA3111D1-Q1 Datenblatt(HTML) 3 Page - Texas Instruments |
3 / 31 page Thermal Pad 1 SD 28 PVCC 2 FAULT 27 PVCC 3 GND 26 BSN 4 GND 25 OUTN 5 GAIN0 24 PGND 6 GAIN1 23 OUTN 7 AVCC 22 BSN 8 AGND 21 BSP 9 GVDD 20 OUTP 10 PLIMIT 19 PGND 11 INN 18 OUTP 12 INP 17 BSP 13 NC 16 PVCC 14 AVCC 15 PVCC TPA3111D1-Q1 www.ti.com SLOS759E – MARCH 2012 – REVISED DECEMBER 2015 5 Pin Configuration and Functions PWP Package 28-Pin HSSOP With PowerPAD™ Top View Pin Functions PIN TYPE DESCRIPTION NAME NO. AGND 8 — Analog supply ground, connect to the thermal pad. AVCC 7 P Analog supply AVCC 14 P Connect AVCC supply to this pin BSN 22, 26 I Bootstrap I/O for negative high-side FET BSP 17, 21 I Bootstrap I/O for positive high-side FET Open drain output used to display short circuit or DC-detect fault status. Voltage compliant to AVCC. Short FAULT 2 O circuit faults can be set to auto-recovery by connecting FAULT pin to SD pin. Otherwise both short circuit faults and DC-detect faults must be reset by cycling PVCC. GAIN0 5 I Gain select least significant bit. TTL logic levels with compliance to AVCC. GAIN1 6 I Gain select most significant bit. TTL logic levels with compliance to AVCC. GND 3, 4 — Connect to local ground High-side FET gate drive supply, nominal voltage is 7 V. This pin can also be used as supply for PLIMIT GVDD 9 O divider. Add a 1- μF capacitor to ground at this pin. INN 11 I Negative audio input, biased at 3 V. INP 12 I Positive audio input, biased at 3 V. NC 13 — Not connected OUTN 23, 25 O Class-D H-bridge negative output OUTP 18, 20 O Class-D H-bridge positive output PGND 19, 24 — Power ground for the H-bridges Power limit level adjust. Connect directly to GVDD pin for no power limiting. Add a 1- μF capacitor to PLIMIT 10 I ground at this pin. 15, 16, PVCC P Power supply for H-bridge. PVCC pins are also connected internally. 27, 28 Shutdown logic input for audio amplifier (LOW = outputs Hi-Z, HIGH = outputs enabled). TTL logic levels SD 1 I with compliance to AVCC. Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: TPA3111D1-Q1 |
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