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PEB20571 Datenblatt(PDF) 53 Page - Infineon Technologies AG

Teilenummer PEB20571
Bauteilbeschribung  ICs for Communications
Download  291 Pages
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Hersteller  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

PEB20571 Datenblatt(HTML) 53 Page - Infineon Technologies AG

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DELIC
PEB 20571
Pin Descriptions
Preliminary Data Sheet
2-26
2003-08
Table 2-17
JTAG and Emulation Interface Pins (DELIC-PB)
Pin
No.
Symbol
In (I)
Out (O)
During
Reset
After
Reset
Function
Used for boundary scan according to IEEE 1149.1
54
JTCK
I
I
I
JTAG Test Clock
Provides the clock for JTAG test logic.
Used also for serial emulation interface.
53
TMS
I
I
I
Test Mode Select
A ’0’ to ’1’ transition on this pin is
required to step through the TAP
controller state machine.
52
TDI /
SCANEN
I
I
I
Test Data Input
In the appropriate TAP controller state
test data or a instruction is shifted in via
this line.
Used also for serial emulation interface.
Note: This pin must not be driven to low
on the board during reset and
operation to ensure functioning of
DELIC
SCAN Enable
When both SCANMO and SCANEN are
asserted, the full-scan tests of DELIC
are activated.
Not used during normal operation.
51
TDO
O
O
O
Test Data Output
In the appropriate TAP controller state
test data or an instruction is shifted out
via this line.
Used also for serial emulation interface.


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