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ADM1260ACPZ Datenblatt(PDF) 10 Page - Analog Devices

Teilenummer ADM1260ACPZ
Bauteilbeschribung  Super Sequencer with Interchip Bus and Nonvolatile Fault Recording
Download  71 Pages
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Hersteller  AD [Analog Devices]
Direct Link  http://www.analog.com
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ADM1260
Data Sheet
Rev. 0 | Page 10 of 71
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
23
24
25
26
27
28
29
30
22
21
ADM1260
TOP VIEW
(Not to Scale)
VX1
VX2
VX3
VX4
VX5
VP1
VP2
VP3
VP4
VH
PDO1
PDO2
PDO3
PDO4
PDO5
PDO6
PDO7
PDO8
PDO9
PDO10
NOTES
1. EXPOSED PAD. THIS PAD IS A NO CONNECT (NC). IF POSSIBLE,
SOLDER THIS PAD TO THE BOARD FOR IMPROVED MECHANICAL
STABILITY. THE EXPOSED PAD MAY BE CONNECTED TO GROUND,
THOUGH THIS CONNECTION IS NOT REQUIRED.
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1 to 5
VX1 to VX5 (VXx)
High Impedance Inputs to Supply the Fault Detectors. Fault thresholds can be set from 0.573 V to1.375 V.
Alternatively, use these pins as general-purpose logic inputs.
6 to 9
VP1 to VP4 (VPx)
Low Voltage Inputs to Supply the Fault Detectors. Three input ranges can be set by altering the input
attenuation on a potential divider connected to these pins, the output of which connects to a supply fault
detector. These pins allow thresholds from 2.5 V to 6.0 V, from 1.25 V to 3.00 V, and from 0.573 V to 1.375 V.
10
VH
High Voltage Input to Supply the Fault Detectors. Two input ranges can be set by altering the input
attenuation on a potential divider connected to this pin, the output of which connects to a supply fault
detector. This pin allows thresholds from 6.0 V to 14.4 V and from 2.5 V to 6.0 V.
11
AGND1
Ground Return for Input Attenuators.
12
REFGND1
Ground Return for On-Chip Reference Circuits.
13
REFIN
Reference Input for the ADC. This pin is nominally 2.048 V and must be driven by a reference voltage. Use the
on-board reference by connecting the REFOUT pin to the REFIN pin.
14
REFOUT
Reference Output, 2.048 V. This pin is typically connected to REFIN. Note that the recommended 10 μF capacitor
must be connected between this pin and REFGND.
15 to 20
DAC1 to DAC6
Voltage Output DACs. These pins default to high impedance at power-up.
21 to 30
PDO10 to PDO1
Programmable Driver Outputs.
31
PDOGND1
Ground Return for Driver Outputs.
32
VCCP
Central Charge Pump Voltage of 5.25 V (Positive/Negative). A reservoir capacitor must be connected between
this pin and GND. A 10 μF capacitor is recommended for this purpose.
33
A0
Logic Input 0. This pin sets the seventh bit of the SMBus interface address.
34
A1
Logic Input 1. This pin sets the sixth bit of the SMBus interface address.
35
SCL
SMBus Clock. This pin is a bidirectional, open-drain pin that requires an external pull-up resistor.
36
SDA
SMBus Data. This pin is a bidirectional, open-drain pin that requires an external pull-up resistor.
37
CCL
ICB Clock. This pin is a bidirectional, open-drain pin that requires an external pull-up resistor.
38
CDA
ICB Data. This pin is a bidirectional, open-drain pin that requires an external pull-up resistor.
39
VDDCAP
Device Supply Voltage. This pin is linearly regulated from the highest of the VPx and VH pins to a typical of
4.75 V. Note that the minimum 10 μF capacitor must be connected between this pin and GND.
40
GND1
Supply Ground.
EPAD
Exposed Pad. This pad is a no connect (NC). If possible, solder this pad to the board for improved mechanical
stability. The exposed pad may be connected to ground, though this connection is not required.
1 In a typical application, all ground pins are connected together.


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