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AD1836AS Datenblatt(PDF) 9 Page - Analog Devices

Teilenummer AD1836AS
Bauteilbeschribung  Multichannel 96 kHz Codec
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Direct Link  http://www.analog.com
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PRELIMINARY TECHNICAL DATA
REV. PrC
AD1836
–9–
CLATCH
CCLK
CDATA
COUT
D15
D9
D0
D14
D8
D0
Figure 2. Format of SPI Signal
Clock Signals
The master clock frequency can be selected for 256, 512, or
768 times the sample rate. The default at power-up is 256 fS.
For operation at 96 kHz, the master clock frequency should
stay at the same absolute frequency. For example, if the AD1836
is programmed in 256
× fS mode and operated in the normal
48 kHz 4-channel mode, the frequency of the master-clock
would be 256
× 48 kHz = 12.288 MHz. If the AD1836 is then
switched to 96 kHz operation (via writing to the SPI port), the
frequency of the master-clock should remain at 12.288 MHz
(which is now 128
× f
S).
The internal clock used in the AD1836 is 512
× f
S (48 kHz
mode) or 512
× fS (96 kHz mode). Clock doublers are used to
generate this internal master-clock from the external clocks.
Since clock-doublers have a limited range of operation, it is
recommended that the part be operated in 512
× fS mode if the
desired sampling rates are not at all close to the common audio
sampling rates for which the part was designed.
To maintain the highest performance possible, it is recommended
that the clock jitter of the master clock signal be limited to less
than 300 ps rms, measured using the edge-to-edge technique.
Even at these levels, extra noise or tones may appear in the
DAC outputs if the jitter spectrum contains large spectral peaks.
It is highly recommended that the master clock be generated by
an independent crystal oscillator. In addition, it is especially
important that the clock signal should not be passed through an
FPGA or other large digital chip before being applied to the
AD1836. In most cases this will induce clock jitter due to the
fact that the clock signal is sharing common power and ground
connections with other unrelated digital output signals.
The six DAC channels use a common serial bit clock to clock in
the serial data and a common left-right framing clock. The four
ADC channels output a common serial bit clock and a left-right
framing clock. The clock signals are all synchronous with the
sample rate.
RESET and Power-Down
RESET will power down the chip and set the control registers
to their default settings. After reset is deasserted, an initialization
routine will run inside the AD1836 to clear all memories to zero.
This initialization lasts for approximately 20 LRCLK intervals.
During this time it is recommended that no SPI writes occur.
Serial Control Port
The AD1836 has an SPI-compatible control port to permit
programming the internal control registers for the ADCs and
DACs and for reading the ADC signal level from the internal
peak detectors. The DAC output levels may be independently
programmed by means of an internal digital attenuator adjust-
able in 1024 linear steps.
The SPI control port is a 4-wire serial control port. The format is
similar to the Motorola SPI format except the input data word
is 16-bits wide. Max serial bit clock frequency is 8 MHz and
may be completely asynchronous to the sample rate of the ADCs
and DACs. The following figure shows the format of the SPI
signal. Note that the CCLK should be run continuously and not
stop between SPI transactions.
Power Supply and Voltage Reference
The AD1836 is designed for 5 V supplies. Separate power sup-
ply pins are provided for the analog and digital sections. These
pins should be bypassed with 100 nF ceramic chip capacitors, as
close to the pins as possible, to minimize noise pickup. A bulk
aluminum electrolytic capacitor of at least 22
µF should also be
provided on the same PC board as the codec. For critical appli-
cations, improved performance will be obtained with separate
supplies for the analog and digital sections. If this is not pos-
sible, it is recommended that the analog and digital supplies be
isolated by means of two ferrite beads in series with the bypass
capacitor of each supply. It is important that the analog supply
be as clean as possible.
The internal voltage reference is brought out on Pin 13 (FILTR)
and should be bypassed as close as possible to the chip, with a
parallel combination of 10
µF and 100 nF. The reference volt-
age may be used to bias external op amps to the common-mode
voltage of the analog input and output signal pins. The current
drawn from the VREF pin should be limited to less than 50
µA.
Serial Data Ports—Data Format
The ADC serial data output mode defaults to the popular I
2S
format, where the data is delayed by 1 BCLK interval from the
edge of the LRCLK. By changing Bits 8 and 9 in ADC Control
Register 2, the serial mode can be changed to Right-Justified
(RJ), Left-Justified DSP (DSP) or Left-Justified (LJ). In the RJ
mode, it is necessary to set Bits 6 and 7 to define the width of
the data word.
The DAC serial data input mode defaults to I
2S. By changing
Bits 5, 6, and 7 in DAC Control Register 1, the mode can be
changed to RJ, DSP, LJ, Packed Mode 1 or Packed Mode 2.


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