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MC10319 Datenblatt(PDF) 11 Page - Motorola, Inc |
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MC10319 Datenblatt(HTML) 11 Page - Motorola, Inc |
11 / 20 page MC10319 11 MOTOROLA ANALOG IC DEVICE DATA VIDEO APPLICATIONS The MC10319 is suitable for digitizing video signals directly without signal conditioning, although the standard 1.0 Vpp video signal can be amplified to a 2.0 Vpp signal for slightly better accuracy. Figure 24 shows the input (top trace) and reconstructed output of a standard NTSC test signal, sampled at 25 MSPS, consisting of a sync pulse, 3.58 MHz color burst, a 3.58 MHz signal in a Sin2x envelope, a pulse, a white level signal, and a black level signal. Figure 25 shows a Sin2x pulse that has been digitized and reconstructed at 25 MSPS. The width of the pulse is ≈450 ns at the base. Figure 26 shows an application circuit for digitizing video. 9–Bit A/D Converter Figure 27 shows how two MC10319s can be connected to form a 9–bit converter. In this configuration, the outputs (D7 to D0) of the two 8–bit converters are paralleled. The outputs of one device are active, while the outputs of the other are in the 3–state mode. The selection is made by the Overrange output of the lower MC10319, which controls Enable inputs on the two devices. Additionally, this output provides the 9th bit. The reference ladders are connected in series, providing the 512 steps required for 9 bits. The input voltage range is determined by VRT of the upper MC10319, and VRB of the lower device. A minimum of 1.0 volt is required across each converter. The 500 Ω pot (20 turn cermet) allows for adjustment of the midpoint since the reference resistors of the two MC10319s may not be identical in value. Without the adjustment, a non–equal voltage division would occur, resulting in a nonlinear conversion. If the references are to be symmetrical about ground (e.g., ± 1.0 V), the adjustment can be eliminated, and the midpoint connected to ground. The use of latches on the outputs is optional, depending on the application. 50 MHz, 8–Bit A/D Converter Figure 28 shows how two MC10319s can be connected together in a flip–flop arrangement in order to have an effective conversion speed of 50 MHz. The 74F74 D–type flip–flop provides a 25 MHz clock to each converter, and at the same time, controls the Enables so as to alternately enable and disable the outputs. The Overranges do not have 3–state capability, and so cannot be paralleled. Instead they are OR’d together. The use of latches is optional, and depends on the application. Data should be latched, or written to RAM (in a DMA operation), on the high–to–low transition of the 50 MHz clock. Negative Voltage Regulator In the cases where a negative power supply is not available (neither the – 3.0 to – 6.0 V, nor a higher negative voltage from which to derive it), the circuit of Figure 29 can be used to generate – 5.0 V from the + 5.0 V supply. The PC board space required is small ( ≈ 2.0 in2), and it can be located physically close to the MC10319. The MC34063A is a switching regulator, and in Figure 29 is configured in an inverting mode of operation. The regulator operating specifications are also given. Figure 16. Differential Phase and Gain Test Clock 40 VRB 60 80 100 VRT 2.000 V 1.024 Vpp to Analyzer MC10319 DUT D0 8 74F374 Latch 8 HDS–1250 12–Bit D/A 285.7 mV 571.4 mV (40 IRE) 0 20 – 20 IRE 120 1.429 V (100 IRE) D3 Video Signal (See Below) Video Input Signal 1. Input waveform: 571.4 mVpp, sine wave @ 3.579545 MHz, dc levels as shown above. 2. MC10319 clock at 14.31818 MHz (4x) asynchronous to input. 3. Differential gain: peak–to–peak output @ each IRE level compared to that at 0 IRE. 4. Differential phase: Phase @ each IRE level compared to that @ 0 IRE. |
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