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MC10319DW Datenblatt(PDF) 4 Page - Motorola, Inc |
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MC10319DW Datenblatt(HTML) 4 Page - Motorola, Inc |
4 / 20 page MC10319 4 MOTOROLA ANALOG IC DEVICE DATA TIMING CHARACTERISTICS (TA = 25°C, VCC = + 5.0 V, VEE = – 5.2 V, VRT = + 1.0 V, VRB = – 1.0 V, see System Timing Diagram, Figure 1.) Characteristic Symbol Min Typ Max Unit INPUTS Min Clock Pulse Width – High tCKH – 5.0 – ns Min Clock Pulse Width – Low tCKL – 15 – ns Max Clock Rise, Fall Time tR,F – 100 – ns Clock Frequency fCLK 0 30 25 MHz OUTPUTS New Data Valid from Clock Low tCKDV – 19 – ns Aperture Delay tAD – 4.0 – ns Hold Time tH – 6.0 – ns Data High to 3–State from Enable Low* tEHZ – 27 – ns Data Low to 3–State from Enable Low* tELZ – 18 – ns Data High to 3–State from Enable High* tEHZ – 32 – ns Data Low to 3–State from Enable High* tELZ – 18 – ns Valid Data from Enable High (Pin 20 = 0 V)* tEDV – 15 – ns Valid Data from Enable Low (Pin 19 = 5.0 V)* tEDV – 16 – ns Output Transition Time* (10% to 90%) ttr – 8.0 – ns *See Figure 2 for output loading. PIN FUNCTION DESCRIPTION Fi Pin Di i Function P Suffix DW Suffix Description VRM 1 1 The midpoint of the reference resistor ladder. Bypassing can be done at this point to improve performance at high frequencies. GND 2, 12 16, 22 2, 13, 17 18, 25, 26 Digital ground. The pins should be connected directly together, and through a low impedance path to the power supply. OVR 3 3 Overrange output. Indicates Vin is more positive than VRT 1/2 LSB. This output does not have 3–state capability. D7–D0 4 to 10, 21 4 to 10, 24 Digital Outputs. D7 (Pin 4) is the MSB. D ∅ (Pin 21 or 24) is the LSB. LS–TTL compatible with 3–state capability. VCC(D) 11, 17 11, 12 19, 20 Power supply for the digital section. + 5.0 V, ±10% required. Reference to digital ground. VEE 13 14 Negative power supply. Nominally – 5.2 V, it can range from – 3.0 to – 6.0 V, and must be more negative than VRB by u 1.3 V. Reference to analog ground. Vin 14 15 Signal voltage input. This voltage is compared to the reference to generate a digital equivalent. Input impedance is nominally 16 to 33K in parallel with 36 pF. VCC(A) 15 16 Power supply for the analog section. + 5.0 V, ±10% required. Reference to analog ground. CLK 18 21 Clock input. TTL compatible. EN 19 22 Enable input. TTL compatible, a logic 1 (and EN at a logic 0) enables the data outputs. A logic 0 puts the outputs in a 3–state mode. EN 20 23 Enable input. TTL compatible, a logic 0 (and EN at a logic 1) enables the data outputs. A logic 1 puts the outputs in a 3–state mode. VRB 23 27 The bottom (most negative point) of the internal reference resistor ladder. VRT 24 28 The top (most positive point) of the internal reference resistor ladder. |
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