STK11C68

June 1999

4-24

SRAM WRITE CYCLES #1 & #2

b

Note j:

If W is low when E goes low, the outputs remain in the high-impedance state.

Note k:

E or W must be

≥ V

NO.

SYMBOLS

PARAMETER

STK11C68-20

STK11C68-25

STK11C68-35

STK11C68-45

UNITS

#1

#2

Alt.

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

12

Write Cycle Time

20

25

35

45

ns

13

Write Pulse Width

15

20

25

30

ns

14

Chip Enable to End of Write

15

20

25

30

ns

15

Data Set-up to End of Write

8

10

12

15

ns

16

Data Hold after End of Write

0

0

0

0

ns

17

Address Set-up to End of Write

15

20

25

30

ns

18

Address Set-up to Start of Write

0

0

0

0

ns

19

Address Hold after End of Write

0

0

0

0

ns

20

i, j

Write Enable to Output Disable

7

10

13

15

ns

21

Output Active after End of Write

5

5

5

5

ns

PREVIOUS DATA

DATA OUT

E

ADDRESS

12

W

16

DATA IN

19

13

18

17

DATA VALID

20

15

HIGH IMPEDANCE

21

14

DATA OUT

E

ADDRESS

12

W

DATA IN

13

17

DATA VALID

HIGH IMPEDANCE

14

18

15

19

16