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DAC0854CIN Datenblatt(PDF) 11 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Teilenummer DAC0854CIN
Bauteilbeschribung  8-Bit Voltage-Output
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Hersteller  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

DAC0854CIN Datenblatt(HTML) 11 Page - National Semiconductor (TI)

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Digital Interface (Continued)
Table III lists the instruction set for the READ mode By the
appropriate setting of the global (G) and address (A1 and
A0) bits one can select a specific DAC to be read or one
can read all the DACs in succession starting with DAC 1
The RF bit determines whether the data changes on the
rising or the falling edge of the system clock With the RF
bit high the data changes on the rising edge that occurs 1
clock cycles after the end of the instruction byte With the
RF bit low the data changes on the falling edge that oc-
curs 1 clock cycle after the end of the instruction byte One
can choose to read the data back MSB first or LSB first by
setting the ML bit (See
Figures 3 and 4 )
An asynchronous update of all the DAC outputs can be
achieved by taking AU low The contents of the input regis-
ters are loaded into the DAC registers with the update oc-
curring on the falling edge of AU CS must be held high
during an asynchronous update
All DAC registers will have their contents reset to all zeros
on power up
TABLE III READ MODE Instruction Set
SB
RDWR
G
RF
ML
A1
A0
Description
Bit
1
Bit
2
Bit
3
Bit
4
Bit
5
Bit
6
Bit
7
1
1
0
0
0
0
0
Read DAC 1 LSB first data changes on the falling edge
1
1
0
0
0
0
1
Read DAC 2 LSB first data changes on the falling edge
1
1
0
0
0
1
0
Read DAC 3 LSB first data changes on the falling edge
1
1
0
0
0
1
1
Read DAC 4 LSB first data changes on the falling edge
1
1
0
0
1
0
0
Read DAC 1 MSB first data changes on the falling edge
1
1
0
0
1
0
1
Read DAC 2 MSB first data changes on the falling edge
1
1
0
0
1
1
0
Read DAC 3 MSB first data changes on the falling edge
1
1
0
0
1
1
1
Read DAC 4 MSB first data changes on the falling edge
1
1
0
1
0
0
0
Read DAC 1 LSB first data changes on the rising edge
1
1
0
1
0
0
1
Read DAC 2 LSB first data changes on the rising edge
1
1
0
1
0
1
0
Read DAC 3 LSB first data changes on the rising edge
1
1
0
1
0
1
1
Read DAC 4 LSB first data changes on the rising edge
1
1
0
1
1
0
0
Read DAC 1 MSB first data changes on the rising edge
1
1
0
1
1
0
1
Read DAC 2 MSB first data changes on the rising edge
1
1
0
1
1
1
0
Read DAC 3 MSB first data changes on the rising edge
1
1
0
1
1
1
1
Read DAC 4 MSB first data changes on the rising edge
1
1
1
0
0
1
0
Read all DACs LSB first data changes on the falling edge
1
1
1
0
1
1
0
Read all DACs MSB first data changes on the falling edge
1
1
1
1
0
1
0
Read all DACs LSB first data changes on the rising edge
1
1
1
1
1
1
0
Read all DACs MSB first data changes on the rising edge
Power Fail Function
If a power failure occurs on the system using the DAC0854
then the INT pin will be pulled low on the next power-up
cycle To force this output high again and reset this flag the
CS pin will have to be brought low When this is done the
INT output will be pulled high again via an external 10 kX
pull-up resistor This feature may be used by the microproc-
essor to discard data whose integrity is in question
Power Supplies
The DAC0854 is designed to operate from a a5V (nominal)
supply There are two supply pins AVCC and DVCC These
pins allow separate external bypass capacitors for the ana-
log and digital portions of the circuit To guarantee accurate
conversions the two supply pins should each be bypassed
with a 01 mF ceramic capacitor in parallel with a 10 mF
tantalum capacitor
11


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