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AM1705DPTPA3 Datenblatt(PDF) 1 Page - Texas Instruments |
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AM1705DPTPA3 Datenblatt(HTML) 1 Page - Texas Instruments |
1 / 165 page Product Folder Sample & Buy Technical Documents Tools & Software Support & Community AM1705 www.ti.com SPRS657E – FEBRUARY 2010 – REVISED JUNE 2014 AM1705 ARM® Microprocessor 1 AM1705 ARM Microprocessor 1.1 Features 1 – Dedicated Interrupt Controller • 375- and 456-MHz ARM926EJ-S™ RISC Core – Dedicated Switched Central Resource – 32-Bit and 16-Bit (Thumb®) Instructions • Multimedia Card (MMC)/Secure Digital (SD) Card – Single-Cycle MAC Interface with Secure Data I/O (SDIO) – ARM Jazelle® Technology • Two Master and Slave Inter-Integrated Circuit (I2C – Embedded ICE-RT™ for Real-Time Debug Bus™) • ARM9™ Memory Architecture • USB 2.0 OTG Port with Integrated PHY (USB0) – 16KB of Instruction Cache – USB 2.0 Full-Speed Client – 16KB of Data Cache – USB 2.0 Full- and Low-Speed Host – 8KB of RAM (Vector Table) – End Point 0 (Control) – 64KB of ROM – End Points 1,2,3,4 (Control, Bulk, Interrupt or • Enhanced Direct Memory Access Controller 3 ISOC) RX and TX (EDMA3): • Two Multichannel Audio Serial Ports (McASPs): – 2 Transfer Controllers – Six Clock Zones and 28 Serial Data Pins – 32 Independent DMA Channels – Supports TDM, I2S, and Similar Formats – 8 Quick DMA Channels – FIFO Buffers for Transmit and Receive – Programmable Transfer Burst Size • 10/100 Mbps Ethernet MAC (EMAC): • 128KB of RAM Memory – IEEE 802.3 Compliant (3.3-V I/O Only) • 3.3-V LVCMOS I/Os (Except for USB Interface) – RMII Media-Independent Interface • Two External Memory Interfaces: – Management Data I/O (MDIO) Module – EMIFA • One 64-Bit General-Purpose Timer (Configurable • NOR (8-Bit-Wide Data) as Two 32-Bit Timers) • NAND (8-Bit-Wide Data) • One 64-Bit General-Purpose Watchdog Timer – EMIFB (Configurable as Two 32-Bit General-Purpose • 16-Bit SDRAM with 128-MB Address Space Timers) • Three Configurable 16550-Type UART Modules: • Three Enhanced Pulse Width Modulators – UART0 with Modem Control Signals (eHRPWMs): – 16-Byte FIFO – Dedicated 16-Bit Time-Base Counter with Period and Frequency Control – 16x or 13x Oversampling Option – 6 Single Edge, 6 Dual Edge Symmetric, or 3 – Autoflow Control Signals (CTS, RTS) on UART0 Dual Edge Asymmetric Outputs Only – Dead-Band Generation • Two Serial Peripheral Interfaces (SPIs) Each with One Chip Select – PWM Chopping by High-Frequency Carrier • Programmable Real-Time Unit Subsystem – Trip Zone Input (PRUSS) • Three 32-Bit Enhanced Capture (eCAP) Modules: – Two Independent Programmable Real-Time Unit – Configurable as 3 Capture Inputs or 3 Auxiliary (PRU) Cores Pulse Width Modulator (APWM) Outputs • 32-Bit Load-Store RISC Architecture – Single-Shot Capture of up to Four Event Time- • 4KB of Instruction RAM per Core Stamps • 512 Bytes of Data RAM per Core • Two 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) Modules • PRUSS can be Disabled via Software to Save Power • 176-pin PowerPAD™ Plastic Quad Flat Pack [PTP suffix], 0.5-mm Pin Pitch – Standard Power-Management Mechanism • Commercial, Industrial, or Extended Temperature • Clock Gating • Entire Subsystem Under a Single PSC Clock Gating Domain 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. |
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