LF198QML

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SNOSAH9A – FEBRUARY 2005 – REVISED MARCH 2013

Electrical Characteristics (continued)

The following specifications apply unless otherwise specified.

Sub-

Symbol

Parameter

Conditions

Notes

Min

Max

Unit

groups

Hold Step

-2.0

2.0

mV

1

-5.6

5.6

mV

2, 3

-2.5

2.5

mV

1

-5.6

5.6

mV

2, 3

-2.5

2.5

mV

1

-5.6

5.6

mV

2, 3

Gain Error

0.02

%

1

0.06

%

2, 3

0.00

%

1

5

0.02

%

2, 3

0.00

%

1

5

0.06

%

2, 3

0.00

%

1

5

0.02

%

2, 3

Input Impedance

10.0

G

Ω

1

0.8

G

Ω

2, 3

10.0

G

Ω

1

0.8

G

Ω

2, 3

Output Impedance

2.0

Ω

1

4.0

Ω

2, 3

Capacitor Charging Current

-25

-4.5

mA

1

-25

-3.0

mA

2, 3

4.5

25

mA

1

3.0

25

mA

2, 3

Logic

Logic Pin Current

10

µA

1, 2, 3

"Sample", Logic = 7V

1.0

µA

1

"Hold", Logic = -30V

0.5

µA

2, 3

Input Offset Voltage

-3.5

3.5

mV

1

-6.0

6.0

mV

2, 3

Input Offset Voltage

-1.1

1.1

mV

1

-2.0

2.0

mV

2, 3

Output Short Circuit Current

7.0

20

mA

1

Output Short Circuit Current

-25

-7.0

mA

1

Logic Reference Pin Current

-1.0

1.0

µA

1

"Sample", Logic = 7V

-0.5

5.0

µA

2, 3

10

µA

1, 2, 3

"Hold", Logic = -30V

(2)

Hold step is sensitive to stray capacitive coupling between input logic signals and the hold capacitor. 1 pF, for instance, will create an

additional 0.5 mV step with a 5V logic swing and a 0.01

μF hold capacitor. Magnitude of the hold step is inversely proportional to hold

capacitor value.

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