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LM2512A Datenblatt(PDF) 2 Page - Texas Instruments

Teilenummer LM2512A
Bauteilbeschribung  Mobile Pixel Link RGB Display Interface Serializer
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Hersteller  TI1 [Texas Instruments]
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LM2512A Datenblatt(HTML) 2 Page - Texas Instruments

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LM2512A
SNLS269B – AUGUST 2007 – REVISED MAY 2013
www.ti.com
Pin Descriptions
No.
Description
Pin Name
I/O, Type(1)
of Pins
RGB Serializer
MPL SERIAL BUS PINS
MD[2:0]
3
O, MPL
MPL Data Line Driver
MC
1
O, MPL
MPL Clock Line Driver
SPI INTERFACE and CONFIGURATION PINS
SPI_CSX
1
I,
SPI_Chip Select Input
LVCMOS
SPI port is enabled when: SPI_CSX is Low, PD* is High, and PCLK is static.
SPI_SCL
1
I,
SPI_Clock Input
LVCMOS
SPI_SDA/HS
1
IO,
Multi-function Pin:
LVCMOS
If SPI_CSX is Low, this is the SPI_SDA IO signal. Default is Input. Pin will be an
output for a SPI Read transaction.
See HS description below also.
PD*
1
I,
Power Down Mode Input
LVCMOS
SER is in sleep mode when PD* = Low, SER is enabled when PD* = High
In PD*=L - Sleep mode: SPI interface is OFF, Register settings are RESET, and
LUT data is retained.
RES1
1
I,
Reserved 1 - Tie High (VDDIO) only available on NZK0049A package
LVCMOS
TM
1
I,
Test Mode
LVCMOS
L = Normal Mode, tie to GND
H = Test Mode (Reserved)
NC
1
NA
Not Connected - Leave Open; only on NZK0049A package
VIDEO INTERFACE PINS
PCLK
1
I,
Pixel Clock Input
LVCMOS
Video Signals are latched on the RISING edge.
R[7:0]
24
I,
RGB Data Bus Inputs – Bit 7 is the MSB.
G[7:0]
LVCMOS
B[7:0]
VS
1
I,
Vertical Sync. Input
LVCMOS
This signal is used as a frame start for the Dither block and is required. The
VS signal is serialized unmodified.
SPI_SDA/HS
1
IO,
Multi-function Pin:
LVCMOS
Horizontal Sync. Input (when SPI_CSX = High)
See SPI_SDA description above also.
DE
1
I,
Data Enable Input
LVCMOS
POWER/GROUND PINS
VDDA
1
Power
Power Supply Pin for the PLL (SER) and MPL Interface.
1.6V to 2.0V
VDD
1
Power
Power Supply Pin for the digital core.
1.6V to 2.0V
VDDIO
3
Power
Power Supply Pin for the parallel interface I/Os.
1.6V to 3.0V
VSSA
1
Ground
Ground Pin for PLL (SER) and MPL interface
VSS
1
Ground
Ground Pin for digital core. For SN40A package, this is the large center pad.
VSSIO
4
Ground
Ground Pin for the parallel interface I/Os. For NJM0040A package, this is the large
center pad.
(1)
Note: I = Input, O = Output, IO = Input/Output. Do not float input pins.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
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