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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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DP83934CVUL-20 Datenblatt(PDF) 58 Page - National Semiconductor (TI) |
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DP83934CVUL-20 Datenblatt(HTML) 58 Page - National Semiconductor (TI) |
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58 / 104 page  70 Bus Interface (Continued) TLF11719 – 31 FIGURE 7-4 Bus Request Timing (BMODE e 1) 732 Block Transfers The SONIC-T performs block operations during all bus ac- tions thereby providing efficient transfers to memory The block cycle consists of three parts The first part is the bus acquisition phase as discussed above in which the SONIC-T gains access to the bus Once it has access of the bus the SONIC-T enters the second phase by transferring data tofrom its internal FIFOs or registers fromto memory The SONIC-T transfers data from its FIFOs in either EXACT BLOCK mode or EMPTYFILL EXACT BLOCK mode In this mode the number of words (or long words) transferred during a block transfer is deter- mined by either the Transmit or Receive FIFO thresholds programmed in the Data Configuration Register EMPTYFILL mode In this mode the DMA completely fills the Transmit FIFO during transmission or completely emp- ties the Receive FIFO during reception This allows for greater bus latency When the SONIC-T accesses the Descriptor Areas (ie RRA RDA CDA and TDA) it transfers data between its registers and memory All fields which need to be used are accessed in one block operation Thus the SONIC-T per- forms 4 accesses in the RRA (see Section 5442) 7 ac- cesses in the RDA (see Section 5461) 2 3 or 6 accesses in the TDA (see Section 554) and 4 accesses in the CDA 733 Bus Status The SONIC-T presents three bits of status information on pins S2 – S0 which indicate the type of bus operation the SONIC-T is currently performing (Table 7-1) Bus status is valid when at the falling edge of AS or the rising edge of ADS TABLE 7-1 Bus Status S2 S1 S0 Status 1 1 1 The bus is idle The SONIC-T is not performing any transfers on the bus 1 0 1 The Transmit Descriptor Area (TDA) is currently being accessed 0 0 1 The Transmit Buffer Area (TBA) is currently being read 0 1 1 The Receive Buffer Area (RBA) is currently being written to Only data is being written though not a Source or Destination address 0 1 0 The Receive Buffer Area (RBA) is currently being written to Only the Source or Destination address is being written though 1 1 0 The Receive Resource Area (RRA) is currently being read 1 0 0 The Receive Descriptor Area (RDA) is currently being accessed 0 0 0 The CAM Descriptor Area (CDA) is currently being accessed 58 |
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Ähnliche Beschreibung - DP83934CVUL-20 |
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