DP83934CVUL-20 datasheet(90/104 Pages) NSC

Teilenummer	DP83934CVUL-20

Bauteilbeschribung	MHz SONICTM-T Systems-Oriented Network Interface Controller with Twisted Pair Interface

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90 AC and DC Specifications (Continued)

MEMORY ARBITRATIONSLAVE ACCESS

TLF11719 – 71

Number

Parameter

20 MHz

25 MHz

Units

Min

Max

Min

Max

T56

CS Low Asynchronous Setup to BSCK

87

ns

(Note 2)

T58

MREQ Low Asynchronous Setup to BSCK

87

ns

(Note 2)

T60

MREQ or CS Valid to SMACK Low

1515

bcyc

(Notes 3 4)

T80

MREQ to SMACK High

18

16

ns

T81

BSCK to SMACK Low

22

20

ns

Note 1

Both CS and MREQ must not be asserted concurrently If these signals are successively asserted there must be at least two bus clocks between the

deasserting and asserting edges of these signals

Note 2

It is not necessary to meet the setup times for MREQ or CS since these signals are asynchronously sampled Meeting the setup time for these signals

however makes it possible to use T60 to determine exactly when SMACK will be asserted

Note 3

T60 could range from 1 bus clock minimum to 5 bus clock maximum depending on what state machine the SONIC-T is when the CS or MREQ signal is

asserted This timing is not tested but is guaranteed by design This specification assumes that CS or MREQ is asserted before the falling edge that these signals

are asynchronously clocked in on (see T56 and T58) SAS must have been asserted for this timing to be correct See SAS and CS timing in the Register Read and

Register Write timing specificaitons

Note 4

bcyc e bus clock cycle time (T3)

Note 5

The way in which SMACK is asserted due to CS is not the same as the way in which SMACK is asserted due to MREQ SMACK goes low as a direct result

of the assertion of MREQ whereas for CS SAS must also be driven low (BMODE e 1) or high (BMODE e 0) before SMACK will be asserted This means that

when SMACK is asserted due to MREQ SMACK will remain asserted until MREQ is deasserted Multiple memory accesses can be made to the shared memory

without SMACK ever going high When SMACK is asserted due to CS however SMACK will only remain low as long as SAS is also low (BMODE e 1) or high

(BMODE e 0) SMACK will not remain low throughout multiple register accesses to the SONIC-T because SAS must toggle for each register access This is an

important difference to consider when designing shared memory designs

90

Ähnliche Beschreibung - DP83934CVUL-20

Hersteller	Teilenummer	Datenblatt	Bauteilbeschribung
National Semiconductor ...	DP83936AVUL-20	1Mb / 104P	Full Duplex SONICTM-T Systems-Oriented Network Interface Controller with Twisted Pair Interface
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	DP83916	1Mb / 96P	SONICTM-16 Systems-Oriented Network Interface Controller
Texas Instruments	DP83934	1Mb / 106P	[Old version datasheet] DP83934CVUL-20/25 MHz SONIC(TM)-T Systems-Oriented Network Interface Controller with Twisted Pair Interface
Winbond	W89C926	395Kb / 48P	PCMCIA ETHERNET NETWORK TWISTED PAIR INTERFACE CONTROLLER
National Semiconductor ...	DP83905	1Mb / 80P	AT Local Area Network Twisted-Pair Interface Controller
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Winbond	W89C940	353Kb / 61P	ELANC-PCI (TWISTED-PAIR ETHER-LAN CONTROLLER WITH PCI INTERFACE)
List of Unclassifed Man...	83C694	204Kb / 33P	TWISTED PAIR INTERFACE AND MACHESTER ENCODER/DECODER
SMSC Corporation	83C694D	205Kb / 33P	Twisted-Pair Interface and Manchester Encoder/Decoder

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