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DP83934CVUL-20 Datenblatt(Datasheet) 2 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Teile-Nr. DP83934CVUL-20
Beschreibung  MHz SONICTM-T Systems-Oriented Network Interface Controller with Twisted Pair Interface
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Hersteller  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com
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 2 page
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Table of Contents
10 CONNECTION DIAGRAMS
11 Pin Connection Diagram NationalIntel Mode
12 Pin Connection Diagram Motorola Mode
20 PIN DESCRIPTION
30 FUNCTIONAL DESCRIPTION
31 Twisted Pair Interface Module
32 IEEE 8023 EncoderDecoder (ENDEC) Unit
321 ENDEC Operation
322 Selecting an External ENDEC
33 Media Access Control (MAC) Unit
331 MAC Receive Section
332 MAC Transmit Section
34 Data Width and Byte Ordering
35 FIFO and Control Logic
351 Receive FIFO
352 Transmit FIFO
36 Status and Configuration Registers
37 Bus Interface
38 Loopback and Diagnostics
381 Loopback Procedure
39 Network Management Functions
40 TRANSMITRECEIVE IEEE 8023 FRAME FORMAT
41 Preamble and Start of Frame Delimiter (SFD)
42 Destination Address
43 Source Address
44 LengthType Field
45 Data Field
46 FCS Field
47 MAC (Media Access Control) Conformance
50 BUFFER MANAGEMENT
51 Buffer Management Overview
52 Descriptor Areas
521 Naming Convention for Descriptors
522 Abbreviations
523 Buffer Management Base Addresses
53 Descriptor Data Alignment
54 Receive Buffer Management
541 Receive Resource Area (RRA)
542 Receive Buffer Area (RBA)
543 Receive Descriptor Area (RDA)
544 Receive Buffer Management Initialization
545 Beginning of Reception
546 End of Packet Processing
547 Overflow Conditions
55 Transmit Buffer Management
551 Transmit Descriptor Area (TDA)
552 Transmit Buffer Area (TBA)
553 Preparing to Transmit
554 Dynamically Adding TDA Descriptors
60 SONIC-T REGISTERS
61 The CAM Unit
611 The Load CAM Command
62 StatusControl Registers
63 Register Description
631 Command Register
632 Data Configuration Register
633 Receive Control Register
634 Transmit Control Register
635 Interrupt Mask Register
636 Interrupt Status Register
637 Data Configuration Register 2
638 Transmit Registers
639 Receive Registers
6310 CAM Registers
6311 Tally Counters
6312 General Purpose Timer
6313 Silicon Revision Register
70 BUS INTERFACE
71 Pin Configurations
72 System Configuration
73 Bus Operations
731 Acquiring the Bus
732 Block Transfers
733 Bus Status
734 Bus Mode Compatibility
735 Master Mode Bus Cycles
736 Bus Exceptions (Bus Retry)
737 Slave Mode Bus Cycle
738 On-Chip Memory Arbiter
739 Chip Reset
80 NETWORK INTERFACING
81 Manchester Encoder and Differential Driver
811 Manchester Decoder
812 Collision Translator
813 Oscillator Inputs
814 Power Supply Considerations
82 Twisted Pair Interface Module
90 AC AND DC SPECIFICATIONS
100 AC TIMING TEST CONDITIONS
2




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