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SM320C6713-EP Datenblatt(PDF) 7 Page - Texas Instruments |
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SM320C6713-EP Datenblatt(HTML) 7 Page - Texas Instruments |
7 / 133 page SM320C6713-EP SM320C6713B-EP www.ti.com SGUS049K – AUGUST 2003 – REVISED APRIL 2011 8-11 Oscillator Divider 1 (OSCDIV1) Register Description ....................................................................... 74 10-1 Characteristics of the Power-Down Modes ................................................................................... 84 10-2 C6713/13B Example Boards and Maximum EMIF Speed .................................................................. 87 11-1 Board-Level Timings Example (see ) .......................................................................................... 93 11-2 Timing Requirements for CLKIN ............................................................................................... 94 11-3 Switching Characteristics for CLKOUT2 ...................................................................................... 94 11-4 Switching Characteristics for CLKOUT3 ...................................................................................... 95 11-5 Timing Requirements for ECLKIN ............................................................................................. 95 11-6 Switching Characteristics for ECLKOUT ..................................................................................... 96 11-7 Timing Requirements for Asynchronous Memory Cycles .................................................................. 97 11-8 Switching Characteristics for Asynchronous Memory Cycles ............................................................. 97 11-9 Timing Requirements for Synchronous-Burst SRAM Cycles ............................................................. 100 11-10 Switching Characteristics for Synchronous-Burst SRAM Cycles ........................................................ 100 11-11 Timing Requirements for Synchronous DRAM Cycles .................................................................... 101 11-12 Switching Characteristics for Synchronous DRAM Cycles ............................................................... 101 11-13 Timing Requirements for HOLD/HOLDA Cycles ........................................................................... 106 11-14 Switching Characteristics for HOLD/HOLDA Cycles ...................................................................... 106 11-15 Switching Characteristics for BUSREQ Cycles ............................................................................ 106 11-16 Timing Requirements for RESET ............................................................................................ 107 11-17 Switching Characteristics For RESET ....................................................................................... 107 11-18 Timing Requirements for External Interrupts ............................................................................... 109 11-19 Timing Requirements for McASP ............................................................................................ 110 11-20 Switching Characteristics for McASP ........................................................................................ 110 11-21 Timing Requirements for I 2C ................................................................................................. 113 11-22 Switching Characteristics for I 2C ............................................................................................. 114 11-23 Timing Requirements for Host-Port Interface Cycles ..................................................................... 115 11-24 Switching Characteristics for Host-Port Interface Cycles ................................................................. 116 11-25 Timing Requirements for McBSP ............................................................................................ 119 11-26 Switching Characteristics for McBSP ........................................................................................ 120 11-27 Timing Requirements for FSR When GSYNC = 1 ......................................................................... 121 11-28 Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 .................................................................................................... 121 11-29 Switching Characteristics for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 .................................................................................................... 122 11-30 Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 .................................................................................................... 122 11-31 Switching Characteristics for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 .................................................................................................... 123 11-32 Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 .................................................................................................... 124 11-33 Switching Characteristics for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 .................................................................................................... 124 11-34 Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 ............................. 125 11-35 Switching Characteristics for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 .................................................................................................... 125 11-36 Timing Requirements for Timer Inputs ...................................................................................... 126 11-37 Switching Characteristics for Timer Inputs ................................................................................. 126 11-38 Timing Requirements for GPIO Inputs ...................................................................................... 127 11-39 Switching Characteristics for GPIO Inputs .................................................................................. 127 11-40 Timing Requirements for JTAG Test Port .................................................................................. 128 Copyright © 2003–2011, Texas Instruments Incorporated List of Tables 7 |
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