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74ALVCH16260DGGRG4 Datenblatt(PDF) 1 Page - Texas Instruments

Teilenummer 74ALVCH16260DGGRG4
Bauteilbeschribung  12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS
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Hersteller  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
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74ALVCH16260DGGRG4 Datenblatt(HTML) 1 Page - Texas Instruments

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FEATURES
DESCRIPTION
DGG OR DL PACKAGE
(TOP VIEW)
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OEA
LE1B
2B3
GND
2B2
2B1
VCC
A1
A2
A3
GND
A4
A5
A6
A7
A8
A9
GND
A10
A11
A12
VCC
1B1
1B2
GND
1B3
LE2B
SEL
OE2B
LEA2B
2B4
GND
2B5
2B6
VCC
2B7
2B8
2B9
GND
2B10
2B11
2B12
1B12
1B11
1B10
GND
1B9
1B8
1B7
VCC
1B6
1B5
GND
1B4
LEA1B
OE1B
Address and/or data information can be stored using the internal storage latches. The latch-enable (LE1B, LE2B,
SN74ALVCH16260
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES046G – JULY 1995 – REVISED OCTOBER 2004
Member of the Texas Instruments Widebus™
Family
EPIC™ (Enhanced-Performance Implanted
CMOS) Submicron Process
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Package Options Include Plastic Shrink
Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
This 12-bit to 24-bit multiplexed D-type latch is
designed for 1.65-V to 3.6-V VCC operation.
The SN74ALVCH16260 is used in applications in
which two separate data paths must be multiplexed
onto, or demultiplexed from, a single data path.
Typical
applications
include
multiplexing
and/or
demultiplexing
address
and
data
information
in
microprocessor or bus-interface applications. This
device
also
is
useful
in
memory-interleaving
applications.
Three 12-bit I/O ports (A1-A12, 1B1-1B12, and
2B1-2B12) are available for address and/or data
transfer. The output-enable (OE1B, OE2B, and OEA)
inputs control the bus transceiver functions. The
OE1B and OE2B control signals also allow bank
control in the A-to-B direction.
LEA1B, and LEA2B) inputs are used to control data storage. When the latch-enable input is high, the latch is
transparent. When the latch-enable input goes low, the data present at the inputs is latched and remains latched
until the latch-enable input is returned high.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH16260 is characterized for operation from -40
°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, EPIC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 1995–2004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.


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