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ST16C654 Datenblatt(PDF) 5 Page - Exar Corporation

Teilenummer ST16C654
Bauteilbeschribung  2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
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Hersteller  EXAR [Exar Corporation]
Direct Link  http://www.exar.com
Logo EXAR - Exar Corporation

ST16C654 Datenblatt(HTML) 5 Page - Exar Corporation

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ST16C654/654D




2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
REV. 5.0.0
5
INTA
(IRQ#)
615
12
O
(OD)
When 16/68# pin is at logic 1 for Intel bus interface, this ouput
becomes channel A interrupt output.
7KH RXWSXW VWDWH LV GHILQHG E\
WKH XVHU DQG WKURXJK WKH VRIWZDUH VHWWLQJ RI 0&5>@ ,17$ LV VHW WR
WKH DFWLYH PRGH ZKHQ 0&5>@ LV VHW WR D ORJLF  ,17$ LV VHW WR WKH
WKUHH VWDWH PRGH ZKHQ 0&5>@ LV VHW WR D ORJLF  GHIDXOW  6HH
0&5>@
When 16/68# pin is at logic 0 for Motorola bus interface, this output
becomes device interrupt output (active low, open drain). An exter-
nal pull-up resistor is required for proper operation.
INTB
INTC
INTD
(N.C.)
12
37
43
21
49
55
18
63
69
O
When 16/68# pin is at logic 1 for Intel bus interface, these ouputs
become the interrupt outputs for channels B, C, and D.
7KH RXWSXW
VWDWH LV GHILQHG E\ WKH XVHU WKURXJK WKH VRIWZDUH VHWWLQJ RI 0&5>@
7KH LQWHUUXSW RXWSXWV DUH VHW WR WKH DFWLYH PRGH ZKHQ 0&5>@ LV VHW
WR D ORJLF  DQG DUH VHW WR WKH WKUHH VWDWH PRGH ZKHQ 0&5>@ LV VHW
WR D ORJLF  GHIDXOW  6HH 0&5>@
When 16/68# pin is at logic 0 for Motorola bus interface, these out-
puts are unused and will stay at logic zero level. Leave these out-
puts unconnected.
INTSEL
-
65
87
I
Interrupt Select (active high, input with internal pull-down).
When 16/68# pin is at logic 1 for Intel bus interface, this pin can be
used in conjunction with MCR bit-3 to enable or disable the INT A-D
pins or override MCR bit-3 and enable the interrupt outputs. Inter-
rupt outputs are enabled continuously by making this pin a logic 1.
Making this pin a logic 0 allows MCR bit-3 to enable and disable the
interrupt output pins. In this mode, MCR bit-3 is set to a logic 1 to
enable the continuous output. See MCR bit-3 description for full
detail. This pin must be at logic 0 in the Motorola bus interface
mode. Due to pin limitations on 64 pin packages, this pin is not
available. To cover this limitation, two 64 pin TQFP packages ver-
sions are offered. This pin is bonded to VCC internally in the
ST16C654D so the INT outputs operate in the continuous interrupt
mode. This pin is bonded to GND internally in the ST16C654 and
therefore requires setting MCR bit-3 for enabling the interrupt output
pins.
TXRDYA#
TXRDYB#
TXRDYC#
TXRDYD#
-
-
-
-
-
-
-
-
5
25
56
81
O
UART channels A-D Transmitter Ready
(active low). The outputs
provide the TX FIFO/THR status for transmit channels A-D.
See
Table 5. If these outputs are unused, leave them unconnected.
RXRDYA#
RXRDYB#
RXRDYC#
RXRDYD#
-
-
-
-
-
-
-
-
100
31
50
82
O
UART channels A-D Receiver Ready (active low). This output pro-
vides the RX FIFO/RHR status for receive channels A-D. See
Table 5. If these outputs are unused, leave them unconnected.
TXRDY#
-
39
45
O
Transmitter Ready (active low). This output is a logically ANDed
status of TXRDY# A-D. See Table 5. If this output is unused, leave
it unconnected.
RXRDY#
-
38
44
O
Receiver Ready (active low). This output is a logically ANDed status
of RXRDY# A-D. See Table 5. If this output is unused, leave it
unconnected.
Pin Description
NAME
64-TQFP
PIN #
68-PLCC
PIN#
100-QFP
PIN #
TYPE
DESCRIPTION


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