SN74SSTVF16857

14BIT REGISTERED BUFFER

WITH SSTL_2 INPUTS AND OUTPUTS

SCES411B – AUGUST 2002 – REVISED APRIL 2003

3

POST OFFICE BOX 655303

–0.5 V to 3.6 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

±50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

±50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

±100 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance,

70

°C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65

°C to 150°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES:

1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. This value is limited to 3.6 V maximum.

3. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions (see Note 4)

MIN

NOM

MAX

UNIT

VCC

Supply voltage

VDDQ

2.7

V

V

O tp t s ppl

oltage

PC1600, PC2100, PC2700

2.3

2.7

V

VDDQ

Output supply voltage

PC3200

2.5

2.7

V

V

Reference voltage (V

V

/2)

PC1600, PC2100, PC2700

1.15

1.25

1.35

V

VREF

Reference voltage (VREF = VDDQ/2)

PC3200

1.25

1.3

1.35

V

VI

Input voltage

0

VCC

V

VIH

AC high-level input voltage

Data inputs

VREF+310mV

V

VIL

AC low-level input voltage

Data inputs

VREF–310mV

V

VIH

DC high-level input voltage

Data inputs

VREF+150mV

V

VIL

DC low-level input voltage

Data inputs

VREF–150mV

V

VIH

High-level input voltage

RESET

1.7

V

VIL

Low-level input voltage

RESET

0.7

V

VICR

Common-mode input voltage range

CLK, CLK

0.97

1.53

V

VI(PP) Peak-to-peak input voltage

CLK, CLK

360

mV

IOH

High-level output current

–16

mA

IOL

Low-level output current

16

mA

TA

Operating free-air temperature

0

70

°C

NOTE 4: The RESET input of the device must be held at valid logic voltage levels (not floating) to ensure proper device operation. The differential

inputs must not be floating unless RESET is low. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs,

literature number SCBA004.