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SN74V245 Datenblatt(PDF) 11 Page - Texas Instruments

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Teilenummer SN74V245
Bauteilbeschribung  DSP-SYNC FIRST-IN, FIRST-OUT MEMORY
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Hersteller  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
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SN74V245 Datenblatt(HTML) 11 Page - Texas Instruments

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SN74V245-EP
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SCAS932A – DECEMBER 2012 – REVISED JANUARY 2013
WRITE EXPANSION INPUT (WXI)
This is a dual-purpose pin. For single-device mode, see Table 6 for additional information. WXI is connected to
write expansion out (WXO) of the previous device in the daisy-chain depth-expansion mode.
READ EXPANSION INPUT (RXI)
This is a dual-purpose pin. For single-device mode, see Table 6 for additional information. RXI is connected to
read expansion out (RXO) of the previous device in the daisy-chain depth-expansion mode.
OUTPUTS:
FULL FLAG/INPUT READY (FF/IR)
This is a dual-purpose pin. In FWFT mode, the input ready (IR) function is selected. IR goes low when memory
space is available for writing data. When there is no free space left, IR goes high, inhibiting further write
operations.
In standard mode, the FF function is selected. When the FIFO is full, FF goes low, inhibiting further write
operations. When FF is high, the FIFO is not full. If no reads are performed after a reset, FF goes low after D
writes to the FIFO. D = 4096.
IR goes high after D writes to the FIFO. D = 4097. The additional word in FWFT mode is due to the capacity of
the memory plus output register.
FF/IR is synchronous and updated on the rising edge of WCLK.
EMPTY FLAG/OUTPUT READY (EF/OR)
This is a dual-purpose pin. In FWFT mode, the OR function is selected. OR goes low at the same time the first
word written to an empty FIFO appears valid on the outputs. OR stays low after the RCLK low-to-high transition
that shifts the last word from the FIFO memory to the outputs. OR goes high only with a true read (RCLK with
REN low). The previous data stays at the outputs, indicating that the last word was read. Further data reads are
inhibited until OR goes low again.
In the standard mode, the EF function is selected. When the FIFO is empty, EF goes low, inhibiting further read
operations. When EF is high, the FIFO is not empty.
EF/OR is synchronous and updated on the rising edge of RCLK.
PROGRAMMABLE ALMOST-FULL FLAG (PAF)
PAF goes low when the FIFO reaches the almost-full condition. In FWFT mode, if no reads are performed, PAF
goes low after 4097 - m. Default values for m are in Table 4 and Table 5.
In standard mode, if no reads are performed after reset (RS), PAF goes low after 4096 – m writes. The offset m
is defined in Table 3.
If asynchronous PAF configuration is selected, PAF is asserted low on the low-to-high transition of WCLK. PAF is
reset to high on the low-to-high transition of RCLK. If synchronous PAF configuration is selected (see Table 6),
PAF is updated on the rising edge of WCLK.
PROGRAMMABLE ALMOST-EMPTY FLAG (PAE)
PAE goes low when the FIFO reaches the almost-empty condition. In FWFT mode, PAE goes low when there
are n + 1 words, or fewer, in the FIFO. In standard mode, PAE goes low when there are n words or fewer in the
FIFO. The offset n is defined as the empty offset. The default values for n are noted in Table 4 and Table 5.
If there is no empty offset specified, PAE is low when the device is 127 away from completely empty.
If asynchronous PAE configuration is selected, PAE is asserted low on the low-to-high transition of the read clock
(RCLK). PAE is reset to high on the low-to-high transition of the write clock (WCLK). If synchronous PAE
configuration is selected (see Table 6), PAE is updated on the rising edge of RCLK.
Copyright © 2012–2013, Texas Instruments Incorporated
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