Datenblatt-Suchmaschine für elektronische Bauteile |
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TL16C552FNRG4 Datenblatt(PDF) 7 Page - Texas Instruments |
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TL16C552FNRG4 Datenblatt(HTML) 7 Page - Texas Instruments |
7 / 33 page TL16C552 DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS102B − DECEMBER 1990 − REVISED MARCH 1996 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 write cycle timing requirements over recommended ranges of operating free-air temperature and supply voltage (see Figure 5) MIN MAX UNIT tw5 Pulse duration, IOW low 80 ns tsu4 Setup time, chip select valid before IOW low (see Note 3) 15 ns tsu5 Setup time, A2 − A0 valid before IOW low (see Note 3) 15 ns tsu6 Setup time, D0 − D7 valid before IOW high 15 ns th3 Hold time, A2 − A0 valid after IOW high (see Note 3) 20 ns th4 Hold time, chip select valid after IOW high (see Note 3) 20 ns th5 Hold time, D0 − D7 valid after IOW high 15 ns td3 Delay time, tsu5 + tw5 + td4 175 ns td4 Delay time, IOW high to IOW or IOR low 80 ns NOTE 3: The internal address strobe is always active. read cycle switching characteristics over recommended ranges of operating free-air temperature and supply voltage (see Figure 4) PARAMETER TEST CONDITIONS MIN MAX UNIT tpd1 Propagation delay time from IOR high to BDO high or from IOR low to BDO low CL = 100 pF, See Note 5 60 ns ten Enable time from IOR low to D0 − D7 valid CL = 100 pF, See Note 5 60 ns tdis Disable time from IOR high to D0 − D7 released CL = 100 pF, See Note 5 0 60 ns NOTE 5: VOL and VOH (and the external loading) determine the charge and discharge time. transmitter switching characteristics over recommended ranges of operating free-air temperature and supply voltage (see Figures 6, 7, and 8) PARAMETER TEST CONDITIONS MIN MAX UNIT td5 Delay time, interrupt THRE low to SOUT low at start 8 24 RCLK cycles td6 Delay time, SOUT low at start to interrupt THRE high See Note 6 8 8 RCLK cycles td7 Delay time, IOW (WR THR) high to interrupt THRE high See Note 6 16 32 RCLK cycles td8 Delay time, SOUT low at start to TXRDY low CL = 100 pF 8 RCLK cycles tpd2 Propagation delay time from IOW (WR THR) low to interrupt THRE low CL = 100 pF 140 ns tpd3 Propagation delay time from IOR (RD IIR) high to interrupt THRE low CL = 100 pF 140 ns tpd4 Propagation delay time from IOW (WR THR) high to TXRDY high CL = 100 pF 195 ns NOTE 6: When the transmitter interrupt delay is active, this delay si lengthened by one character time minus the last stop bit time. |
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Ähnliche Beschreibung - TL16C552FNRG4 |
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