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TMP100 Datenblatt(PDF) 9 Page - Texas Instruments |
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TMP100 Datenblatt(HTML) 9 Page - Texas Instruments |
9 / 10 page TMP100, 101 9 SBOS231C www.ti.com HIGH-SPEED MODE In order for the I2C bus to operate at frequencies above 400kHz, the master device must issue an Hs-mode master code (00001XXX) as the first byte after a START condition to switch the bus to high-speed operation. The TMP100 and TMP101 will not acknowledge this byte as required by the I2C specification, but will switch their input filters on SDA and SCL and their output filters on SDA to operate in Hs-mode, allowing transfers at up to 3.4MHz. After the Hs-mode master code has been issued, the master will transmit an I2C slave address to initiate a data transfer operation. The bus will continue to operate in Hs-mode until a STOP condition occurs on the bus. Upon receiving the STOP condition, the TMP100 and TMP101 will switch their input and output filters back to fast-mode operation. TIMING DIAGRAMS The TMP100 and TMP101 are I2C and SMBus compatible. Figures 5 to 8 describe the various operations on the TMP100 and TMP101. Bus definitions are given below. Parameters for Figure 5 are defined in Table XIII. Bus Idle: Both SDA and SCL lines remain HIGH. Start Data Transfer: A change in the state of the SDA line, from HIGH to LOW, while the SCL line is HIGH, defines a START condition. Each data transfer is initiated with a START condition. Stop Data Transfer: A change in the state of the SDA line from LOW to HIGH while the SCL line is HIGH defines a STOP condition. Each data transfer is terminated with a repeated START or STOP condition. Data Transfer: The number of data bytes transferred be- tween a START and a STOP condition is not limited and is determined by the master device. The receiver acknowl- edges the transfer of data. Acknowledge: Each receiving device, when addressed, is obliged to generate an Acknowledge bit. A device that acknowledges must pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the Acknowledge clock pulse. Setup and hold times must be taken into ac- count. On a master receive, the termination of the data transfer can be signaled by the master generating a Not- Acknowledge on the last byte that has been transmitted by the slave. FAST MODE HIGH-SPEED MODE PARAMETER MIN MAX MIN MAX UNITS SCLK Operating Frequency f(SCLK) 0.4 3.4 MHz Bus Free Time Between STOP and START Condition t(BUF) 600 160 ns Hold Time After Repeated START Condition. t(HDSTA) 600 160 ns After this period, the first clock is generated. Repeated START Condition Setup Time t(SUSTA) 600 160 ns STOP Condition Setup Time t(SUSTO) 600 160 ns Data Hold Time t(HDDAT) 00 ns Data Setup Time t(SUDAT) 100 10 ns SCLK Clock LOW Period t(LOW) 1300 160 ns SCLK Clock HIGH Period t(HIGH) 600 60 ns Clock/Data Fall Time tF 300 160 ns Clock/Data Rise Time tR 300 160 ns TABLE XIII. Timing Diagram Definitions. |
Ähnliche Teilenummer - TMP100 |
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Ähnliche Beschreibung - TMP100 |
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