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LF11331D Datenblatt(PDF) 8 Page - National Semiconductor (TI) |
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LF11331D Datenblatt(HTML) 8 Page - National Semiconductor (TI) |
8 / 18 page Typical Performance Characteristics (Continued) Application Hints GENERAL INFORMATION These devices are monolithic quad JFET analog switches with “ON” resistances which are essentially independent of analog voltage or analog current. The leakage currents are typically less than 1 nA at 25˚C in both the “OFF”and “ON” switch states and introduce negligible errors in most applica- tions. Each switch is controlled by minimum TTL logic levels at its input and is designed to turn “OFF” faster than it will turn “ON.” This prevents two analog sources from being tran- siently connected together during switching. The switches were designed for applications which require break-before-make action, no analog current loss, medium speed switching times and moderate analog currents. Because these analog switches are JFET rather than CMOS, they do not require special handling. LOGIC INPUTS The logic input (IN), of each switch, is referenced to two for- ward diode drops (1.4V at 25˚C) from the reference supply (V R) which makes it compatible with DTL, RTL, and TTL logic families. For normal operation, the logic “0” voltage can range from 0.8V to −4.0V with respect to V R and the logic “1” voltage can range from 2.0V to 6.0V with respect to V R, pro- vided V IN is not greater than (VCC−2.5V). If the input voltage is greater than (V CC−2.5V), the input current will increase. If the input voltage exceeds 6.0V or −4.0V with respect to V R, a resistor in series with the input should be used to limit the input current to less than 100µA. ANALOG VOLTAGE AND CURRENT Analog Voltage Each switch has a constant “ON” resistance (R ON) for analog voltages from (V EE+5V) to (VCC−5V). For analog voltages greater than (V CC−5V), the switch will remain ON indepen- dent of the logic input voltage. For analog voltages less than (V EE+5V), the ON resistance of the switch will increase. Al- though the switch will not operate normally when the analog voltage is out of the previously mentioned range, the source voltage can go to either (V EE+36V) or (VCC+6V), whichever is more positive, and can go as negative as V EE without de- struction. The drain (D) voltage can also go to either (V EE+36V) or (VCC+6V), whichever is more positive, and can go as negative as (V CC−36V) without destruction. Analog Current With the source (S) positive with respect to the drain (D), the R ON is constant for low analog currents, but will increase at higher currents (>5 mA) when the FET enters the saturation region. However, if the drain is positive with respect to the source and a small analog current loss at high analog cur- rents (Note 6) is tolerable, a low R ON can be maintained for analog currents greater than 5 mA at 25˚C. Slew Rate of Analog Voltage Above Which Signal Loading Occurs DS005667-35 Small Signal Response DS005667-36 Maximum Accurate Analog Current vs Temperature DS005667-37 Logical “1” Input Bias Current DS005667-38 www.national.com 8 |
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Ähnliche Beschreibung - LF11331D |
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