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MC10E111FNG Datenblatt(PDF) 6 Page - ON Semiconductor

Teilenummer MC10E111FNG
Bauteilbeschribung  5V ECL 1:9 Differential Clock Driver
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Hersteller  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
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MC10E111FNG Datenblatt(HTML) 6 Page - ON Semiconductor

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MC10E111, MC100E111
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6
Table 7. AC CHARACTERISTICS (VCCx = 5.0 V; VEE= 0.0 V or VCCx = 0.0 V; VEE= −5.0 V (Note 1))
Symbol
Unit
85°C
25°C
−40°C
Characteristic
Symbol
Unit
Max
Typ
Min
Max
Typ
Min
Max
Typ
Min
Characteristic
tskew
Within-Device Skew (Note 8)
25
75
25
50
25
50
ps
tJITTER
Random Clock Jitter (RMS)
<1
<2
<1
<2
<1
<2
ps
VPP
Minimum Input Swing
50
50
50
mV
tr, tf
Rise/Fall Time
250
450
650
275
375
600
275
375
600
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
1. 10 Series: VEE can vary −0.46 V / +0.06 V.
100 Series: VEE can vary −0.46 / +0.8 V.
2. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of
the differential output signals.
3. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal.
4. Enable is defined as the propagation delay from the 50% point of a negative transition on EN to the 50% point of a positive transition
on Q (or a negative transition on Q). Disable is defined as the propagation delay from the 50% point of a positive transition on EN to the
50% point of a negative transition on Q (or a positive transition on Q).
5. The setup time is the minimum time that EN must be asserted prior to the next transition of IN/IN to prevent an output response greater
than $75 mV to that IN/IN transition (Figure 3).
6. The hold time is the minimum time that EN must remain asserted after a negative going IN or a positive going IN to prevent an output
response greater than $75 mV to that IN/IN transition (Figure 4).
7. The release time is the minimum time that EN must be deasserted prior to the next IN/IN transition to ensure an output response that meets
the specified IN to Q propagation delay and output transition times (Figure 5).
8. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device.
Figure 3. Setup Time
ts
IN
IN
EN
Q
≤ 75mV
≤ 75mV
Q
≤ 75mV
≤ 75mV
Figure 4. Hold Time
th
IN
IN
EN
Q
Q
Figure 5. Release Time
tr
IN
IN
EN
50%
Q
Q
50%
50%


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