MYSON

TECHNOLOGY

MTV012E

MTV012E Revision 1.2 12/23/1998

11/14

timer function is disabled after power-on reset; the user can activate this function by setting WEN, and

clear the timer by setting WCLR.

reg name

addr

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

MSTUS

00h (r)

X

SCLERR

DDC2

BERR

HFREQ

FIFOH

FIFOL

BUSY

MBUF

10h (r/w)

MBUF7

MBUF6

MBUF5

MBUF4

MBUF3

MBUF2

MBUF1

MBUF0

INTFLG

50h (r/w)

HPRchg

VPRchg

HPLchg

VPLchg

HFchg

VFchg

FIFOI

MI

MCTR

00h (w)

LS1

LS0

LDFIFO

M256

M128

ACK

P

S

INTEN

60h (w)

EHPR

EVPR

EHPL

EVPL

EHF

EVF

EFIFO

EMI

FIFO

70h (w)

FIFO7

FIFO6

FIFO5

FIFO4

FIFO3

FIFO2

FIFO1

FIFO0

WDT

80h (w)

WEN

WCLR

CLRDDC

DIV253

LVSEL

WDT2

WDT1

WDT0

SLVCTR

90h (w)

ENSLV

SLVsel

ESLVBI

ESLVMI

X

X

X

X

SLVSTUS

91h (r)

WADR

SLVS

SLVBI

SLVMI

X

X

X

X

SLVINT

91h (w)

X

X

X

SLVMI

X

X

X

X

SLVBUF

92h (r)

SLVbuf7

SLVbuf6

SLVbuf5

SLVbuf4

SLVbuf3

SLVbuf2

SLVbuf1

SLVbuf0

SLVADR

93h (w)

SLVadr7

SLVadr6

SLVadr5

SLVadr4

SLVadr3

SLVadr2

SLVadr1

X

MCTR (w) :

Master IIC interface control register.

LS1, LS0

= 11

→ FIFOL is the status which has a FIFO depth of < 5.

= 10

→ FIFOL is the status which has a FIFO depth of < 4.

= 01

→ FIFOL is the status which has a FIFO depth of < 3.

= 00

→ FIFOL is the status which has a FIFO depth of < 2.

LDFIFO

= 1

→ FIFO will be written while S/W reads MBUF.

M256

= 1

→ Disables host writing EEPROM when address is over 256.

M128

= 1

→ Disables host writing EEPROM when address is over 128.

ACK

= 1

→ In receiving mode, there is no acknowledgment by MTV012E.

= 0

→ In receiving mode, ACK is returned by MTV012E.

S, P

=

↑,0

→ Start condition when Master IIC is not transferring.

= X,

↑ → Stop condition when Master IIC is not transferring.

= 1,X

→ Will resume transfer after a read/write MBUF operation.

= X,0

→ Forces HSCL low and occupies the IIC bus.

* MTV012E uses a 100KHz clock to sample the S/P bit; any pulse should sustain at least 20us.

* A write/read MBUF operation can be recognized only after 10us of the MI flag's rising edge.

MSTUS (r) :

Master IIC interface status register.

SCLERR

= 1

→ The ISCL pin is pulled-low by other devices during the

transfer, and cleared when S=0.

DDC2

= 1

→ DDC2B is active.

= 0

→ MTV012E remains in DDC1 mode.

BERR

= 1

→ IIC bus error, no ACK received from the slave, updated every time

when slave sends ACK on the ISDA pin.

HFREQ

= 1

→ MTV012E detects a higher than 200Hz clock on the VSYNC pin.

FIFOH

= 1

→ FIFO high indicated.

FIFOL

= 1

→ FIFO low indicated.

BUSY

= 1

→ Host drives the HSCL pin to low.

* While writing FIFO, the FIFOH/FIFOL flag will reflect the FIFO condition after 30us.

INTFLG (w) :

Interrupt flag. An interrupt event will set its individual flag and, if the corresponding

interrupt enable bit is set, the 8051 INT1 source will be driven by a zero level. Software

MUST clear this register while serving the interrupt routine.

FIFOI

= 1

→ No action.

= 0

→ Clears FIFOI flag.

MI

= 1

→ No action.

= 0

→ Clears Master IIC bus interrupt flag (MI).