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ADF4360-3BCP Datenblatt(PDF) 9 Page - Analog Devices |
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ADF4360-3BCP Datenblatt(HTML) 9 Page - Analog Devices |
9 / 20 page PRELIMINARY TECHNICAL DATA ADF4360-2 REV. PrA 07/03 –9– VCO The VCO core in the ADF4360 family uses eight overlapping bands as shown in figure 6 to allow a wide frequency range to be covered without a large VCO sensitivity (Kv) and resultant poor phase noise and spurious performance. The correct band is chosen automatically by the band select logic at power-up or whenever the N Counter latch is updated. It is important that the correct write sequence be followed at power-up. This sequence is: 1) R Counter latch 2) Control latch 3) N Counter latch During band select, which takes five PFD cycles, The VCO Vtune is disconnected from the output of the loop filter and connected to an internal reference voltage. The operating current in the VCO core is programmable in four steps, 5mA, 10mA, 15mA & 20mA. This is controlled by bits PC1 & PC2 in the Control latch. OUTPUT STAGE The RFoutA and RFoutB pins of the ADF4360 family are connected to the collectors of an NPN differential pair driven by buffered outputs of the VCO as shown in figure 7. To allow the user to optimise his/her power dissipation vs output power requirements, The tail current of the differential pair is programmable via bits PL1 & PL2 in the Control latch. Four current levels may be set; 3.5mA, 5mA, 7.5mA and 11mA giving output power levels of - 13dBm, -10.5dBm, -8dBm & -6dBm using a 50Ohm resistor to Vdd and ac-coupling into a 50Ohm load. Alternatively, both outputs can be combined in a 1+1:1 transformer or a 180 microstrip coupler. See Page 19. If the outputs are to be used individually, then the optimum output stage consists of a shunt inductor to Vdd. Another feature of the ADF4360 family is provided whereby the supply current to the RF output stage is shut down until the part achieves lock as measured by the Digital Lock Detect circuitry. This is enabled by the MTLD (Mute Till Lock Detect) bit in the Control latch. Figure 6 Frequency vs Vtune, ADF4360-2 After band select, normal PLL action resumes. The nominal value of Kv is 57MHz/Volt or 28MHZ/Volt if divide by two operation has been selected (by programming DIVSEL (DB22), high in the N Counter latch). The ADF4360 family contains linearisation circuitry to minimise any variation of the product of Icp and Kv. The R Counter output is used as the clock for the band select logic and should not exceed 1MHz. A programmable divider is provided at the R Counter input to allow division by 1,2,4 or 8, and is controlled by bits BSC1 and BSC2 in the R Counter Latch. Where the required PFD frequency exceeds 1 MHz the divide ratio should be set to allow enough time for correct band selection. VCO BUFFER / DIVIDE BY 2 RFOUTA RFOUTB Figure 7 RF Output Stage ADF4360-2 |
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Ähnliche Beschreibung - ADF4360-3BCP |
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