Datenblatt-Suchmaschine für elektronische Bauteile |
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M02050-15 Datenblatt(PDF) 11 Page - List of Unclassifed Manufacturers |
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M02050-15 Datenblatt(HTML) 11 Page - List of Unclassifed Manufacturers |
11 / 28 page Functional Description 02050-DSH-002-F Mindspeed Technologies™ 9 Mindspeed Proprietary and Confidential 3.2 Features • Operates with a 3.3V or 5V supply • 3.5 mV typical input sensitivity at 2.5 Gbps • PECL outputs • Rate Selection for ≤ 1.25 Gbps operation • Average Receive power monitor output (RSSIAVG) • Peak-to-peak Receive power monitor output (RSSIPP) • On-chip DC offset cancellation circuit • Low power (< 180 mW at 3.3V) • Output Jam Function • 16 pin 3x3 QFN package 3.3 General Description The M02050-15 is a high-gain limiting amplifier for applications up to 2.5 Gbps, and incorporates a limiting ampli- fier, an input signal level detection circuit and also a fully integrated DC-offset cancellation loop that does not require any external components. The M02050-15 features PECL data outputs. The M02050-15 provides the user with the flexibility to set the signal detect threshold. Optional output buffer dis- able (squelch/jam) can be implemented using the JAM input. 3.3.1 Inputs The data inputs are internally connected to VTT via 50 Ω resistors, and generally need to be AC coupled. Referring to Figure 3-2, the nominal VTT voltage is 2.85V because of the internal resistor divider to VCC3, which means this is the DC potential on the data inputs. See the applications information section for further details on choosing the AC- coupling capacitor. Figure 3-2. CML Data Inputs VCC3 50 Ω DINP VTT 50 Ω DINN 8.3 k Ω 1.3 k Ω V CC VCC |
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Ähnliche Beschreibung - M02050-15 |
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