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GS7005-CTT Datenblatt(PDF) 3 Page - Gennum Corporation

Teilenummer GS7005-CTT
Bauteilbeschribung  Complete Serial Digital Video Receiver
Download  12 Pages
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Hersteller  GENNUM [Gennum Corporation]
Direct Link  http://www.gennum.com
Logo GENNUM - Gennum Corporation

GS7005-CTT Datenblatt(HTML) 3 Page - Gennum Corporation

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GENNUM CORPORATION
522 - 14 - 06
3
AC ELECTRICAL CHARACTERISTICS
VCC = 5V, TA = 25°C, unless otherwise specified in ‘conditions’
Serial data rate = 270Mb/s, Parallel Data Rate = 27Mb/s, ƒPCLK = 27MHz
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
NOTE
S
TEST
LEVEL
Parallel Data - Rise/Fall Time
tR/F_DOUT
CL = 20pF
1.0
-
6.0
ns
1
4, 7
PCLK Rising Edge to DOUT(N) Centre
tD
-
-
±5
ns
2, 3
4, 7
PCLK Rise/Fall Time
tR/F_PCLKOUT
CL = 20pF
0.5
-
3.0
ns
1
4, 7
Input Return Loss
LOSSIN
75
Ω match
5MHz to 270MHz
-17
-
dB
7
Asynchronous Lock Time
tLOCK_ASYNC
-
-
250
ms
4
1
Synchronous Lock Time
tLOCK_SYNC
-
-
10
µs
5
1
Input Jitter Tolerance
tJ_SI
Pathological Input
-
0.35
-
U.I.
6
7
Output PCLK Jitter
tJ_PCLKOUT
Pseudorandom
Input
-
800
-
ps p-p
1
Pathological Input
-
1000
-
ps p-p
6
7
Error Free Cable Length
Pseudorandom
Input
-
100
-
m
7
Pathological Input
75
100
-
m
6, 7
1
NOTES
1. Rise/Fall time is defined as the time for the signal to rise from 20% to 80% of the specified p-p value, or to fall from 80% to 20% of the
specified value.
2. Refer also to Figure 10.
3. This is the time difference between the rising edge of PCLKOUT and the centre of the bit period.
4. This is the time delay between a valid serial TRS signal on the input to the moment valid data appears on the parallel outputs.
5. This is the time for the PLL to re-lock when video streams are switched during the vertical blanking interval in accordance with SMPTE
RP168-1993. The two streams may be 180° out of phase with respect to one another, but pixel aligned.
6. This pathological pattern is defined in SMPTE RP178-1996, paragraphs 4.1 and 4.3.
7. "Error free" is defined as no single bit errors over a period of 10 minutes, using Belden 8281 Cable and 75
Ω connections. The MIN
value is fully tested and the TYP value is based on using the EB7005 Evaluation Board.
TEST LEVELS
1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges.
2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated
test.
3. Production test at room temperature and nominal supply voltage.
4. QA sample test.
5. Calculated result based on Level 1,2, or 3.
6. Not tested. Guaranteed by design simulations.
7. Not tested. Based on characterization of nominal parts.
8. Not tested. Based on existing design/characterization data of similar product.


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